1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <libfdt.h> 12 #include <altera.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <watchdog.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/arch/scu.h> 22 #include <asm/pl310.h> 23 24 #include <dt-bindings/reset/altr,rst-mgr.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct pl310_regs *const pl310 = 29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 30 static struct socfpga_system_manager *sysmgr_regs = 31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 32 static struct socfpga_reset_manager *reset_manager_base = 33 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; 34 static struct nic301_registers *nic301_regs = 35 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 36 static struct scu_registers *scu_regs = 37 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 38 39 int dram_init(void) 40 { 41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 42 return 0; 43 } 44 45 void enable_caches(void) 46 { 47 #ifndef CONFIG_SYS_ICACHE_OFF 48 icache_enable(); 49 #endif 50 #ifndef CONFIG_SYS_DCACHE_OFF 51 dcache_enable(); 52 #endif 53 } 54 55 void v7_outer_cache_enable(void) 56 { 57 /* disable the L2 cache */ 58 writel(0, &pl310->pl310_ctrl); 59 60 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 61 setbits_le32(&pl310->pl310_aux_ctrl, 62 L310_AUX_CTRL_DATA_PREFETCH_MASK | 63 L310_AUX_CTRL_INST_PREFETCH_MASK | 64 L310_SHARED_ATT_OVERRIDE_ENABLE); 65 } 66 67 /* 68 * DesignWare Ethernet initialization 69 */ 70 #ifdef CONFIG_ETH_DESIGNWARE 71 static void dwmac_deassert_reset(const unsigned int of_reset_id) 72 { 73 u32 physhift, reset; 74 75 if (of_reset_id == EMAC0_RESET) { 76 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 77 reset = SOCFPGA_RESET(EMAC0); 78 } else if (of_reset_id == EMAC1_RESET) { 79 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 80 reset = SOCFPGA_RESET(EMAC1); 81 } else { 82 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 83 return; 84 } 85 86 /* Clearing emac0 PHY interface select to 0 */ 87 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 88 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 89 90 /* configure to PHY interface select choosed */ 91 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 92 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 93 94 /* Release the EMAC controller from reset */ 95 socfpga_per_reset(reset, 0); 96 } 97 98 int cpu_eth_init(bd_t *bis) 99 { 100 const void *fdt = gd->fdt_blob; 101 struct fdtdec_phandle_args args; 102 int nodes[2]; /* Max. two GMACs */ 103 int ret, count; 104 int i, node; 105 106 /* Put both GMACs into RESET state. */ 107 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 108 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 109 110 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 111 COMPAT_ALTERA_SOCFPGA_DWMAC, 112 nodes, ARRAY_SIZE(nodes)); 113 for (i = 0; i < count; i++) { 114 node = nodes[i]; 115 if (node <= 0) 116 continue; 117 118 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 119 "#reset-cells", 1, 0, 120 &args); 121 if (ret || (args.args_count != 1)) { 122 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 123 continue; 124 } 125 126 dwmac_deassert_reset(args.args[0]); 127 } 128 129 return 0; 130 } 131 #endif 132 133 #ifdef CONFIG_DWMMC 134 /* 135 * Initializes MMC controllers. 136 * to override, implement board_mmc_init() 137 */ 138 int cpu_mmc_init(bd_t *bis) 139 { 140 return socfpga_dwmmc_init(gd->fdt_blob); 141 } 142 #endif 143 144 struct { 145 const char *mode; 146 const char *name; 147 } bsel_str[] = { 148 { "rsvd", "Reserved", }, 149 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 150 { "nand", "NAND Flash (1.8V)", }, 151 { "nand", "NAND Flash (3.0V)", }, 152 { "sd", "SD/MMC External Transceiver (1.8V)", }, 153 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 154 { "qspi", "QSPI Flash (1.8V)", }, 155 { "qspi", "QSPI Flash (3.0V)", }, 156 }; 157 158 static const struct { 159 const u16 pn; 160 const char *name; 161 const char *var; 162 } const socfpga_fpga_model[] = { 163 /* Cyclone V E */ 164 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, 165 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, 166 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, 167 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, 168 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, 169 /* Cyclone V GX/GT */ 170 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, 171 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, 172 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, 173 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, 174 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, 175 /* Cyclone V SE/SX/ST */ 176 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, 177 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, 178 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, 179 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, 180 /* Arria V */ 181 { 0x2d03, "Arria V, D5", "av_d5" }, 182 }; 183 184 static int socfpga_fpga_id(const bool print_id) 185 { 186 const u32 altera_mi = 0x6e; 187 const u32 id = scan_mgr_get_fpga_id(); 188 189 const u32 lsb = id & 0x00000001; 190 const u32 mi = (id >> 1) & 0x000007ff; 191 const u32 pn = (id >> 12) & 0x0000ffff; 192 const u32 version = (id >> 28) & 0x0000000f; 193 int i; 194 195 if ((mi != altera_mi) || (lsb != 1)) { 196 printf("FPGA: Not Altera chip ID\n"); 197 return -EINVAL; 198 } 199 200 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) 201 if (pn == socfpga_fpga_model[i].pn) 202 break; 203 204 if (i == ARRAY_SIZE(socfpga_fpga_model)) { 205 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); 206 return -EINVAL; 207 } 208 209 if (print_id) 210 printf("FPGA: Altera %s, version 0x%01x\n", 211 socfpga_fpga_model[i].name, version); 212 return i; 213 } 214 215 /* 216 * Print CPU information 217 */ 218 #if defined(CONFIG_DISPLAY_CPUINFO) 219 int print_cpuinfo(void) 220 { 221 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 222 puts("CPU: Altera SoCFPGA Platform\n"); 223 socfpga_fpga_id(1); 224 printf("BOOT: %s\n", bsel_str[bsel].name); 225 return 0; 226 } 227 #endif 228 229 #ifdef CONFIG_ARCH_MISC_INIT 230 int arch_misc_init(void) 231 { 232 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; 233 const int fpga_id = socfpga_fpga_id(0); 234 setenv("bootmode", bsel_str[bsel].mode); 235 if (fpga_id >= 0) 236 setenv("fpgatype", socfpga_fpga_model[fpga_id].var); 237 return 0; 238 } 239 #endif 240 241 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 242 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 243 int overwrite_console(void) 244 { 245 return 0; 246 } 247 #endif 248 249 #ifdef CONFIG_FPGA 250 /* 251 * FPGA programming support for SoC FPGA Cyclone V 252 */ 253 static Altera_desc altera_fpga[] = { 254 { 255 /* Family */ 256 Altera_SoCFPGA, 257 /* Interface type */ 258 fast_passive_parallel, 259 /* No limitation as additional data will be ignored */ 260 -1, 261 /* No device function table */ 262 NULL, 263 /* Base interface address specified in driver */ 264 NULL, 265 /* No cookie implementation */ 266 0 267 }, 268 }; 269 270 /* add device descriptor to FPGA device table */ 271 static void socfpga_fpga_add(void) 272 { 273 int i; 274 fpga_init(); 275 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 276 fpga_add(fpga_altera, &altera_fpga[i]); 277 } 278 #else 279 static inline void socfpga_fpga_add(void) {} 280 #endif 281 282 int arch_cpu_init(void) 283 { 284 #ifdef CONFIG_HW_WATCHDOG 285 /* 286 * In case the watchdog is enabled, make sure to (re-)configure it 287 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 288 * timeout value is still active which might too short for Linux 289 * booting. 290 */ 291 hw_watchdog_init(); 292 #else 293 /* 294 * If the HW watchdog is NOT enabled, make sure it is not running, 295 * for example because it was enabled in the preloader. This might 296 * trigger a watchdog-triggered reboot of Linux kernel later. 297 * Toggle watchdog reset, so watchdog in not running state. 298 */ 299 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 300 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 301 #endif 302 303 return 0; 304 } 305 306 /* 307 * Convert all NIC-301 AMBA slaves from secure to non-secure 308 */ 309 static void socfpga_nic301_slave_ns(void) 310 { 311 writel(0x1, &nic301_regs->lwhps2fpgaregs); 312 writel(0x1, &nic301_regs->hps2fpgaregs); 313 writel(0x1, &nic301_regs->acp); 314 writel(0x1, &nic301_regs->rom); 315 writel(0x1, &nic301_regs->ocram); 316 writel(0x1, &nic301_regs->sdrdata); 317 } 318 319 static uint32_t iswgrp_handoff[8]; 320 321 int arch_early_init_r(void) 322 { 323 int i; 324 325 /* 326 * Write magic value into magic register to unlock support for 327 * issuing warm reset. The ancient kernel code expects this 328 * value to be written into the register by the bootloader, so 329 * to support that old code, we write it here instead of in the 330 * reset_cpu() function just before reseting the CPU. 331 */ 332 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); 333 334 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ 335 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); 336 337 socfpga_bridges_reset(1); 338 socfpga_nic301_slave_ns(); 339 340 /* 341 * Private components security: 342 * U-Boot : configure private timer, global timer and cpu component 343 * access as non secure for kernel stage (as required by Linux) 344 */ 345 setbits_le32(&scu_regs->sacr, 0xfff); 346 347 /* Configure the L2 controller to make SDRAM start at 0 */ 348 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 349 writel(0x2, &nic301_regs->remap); 350 #else 351 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 352 writel(0x1, &pl310->pl310_addr_filter_start); 353 #endif 354 355 /* Add device descriptor to FPGA device table */ 356 socfpga_fpga_add(); 357 358 #ifdef CONFIG_DESIGNWARE_SPI 359 /* Get Designware SPI controller out of reset */ 360 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); 361 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); 362 #endif 363 364 return 0; 365 } 366 367 static void socfpga_sdram_apply_static_cfg(void) 368 { 369 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; 370 const uint32_t applymask = 0x8; 371 uint32_t val = readl(staticcfg) | applymask; 372 373 /* 374 * SDRAM staticcfg register specific: 375 * When applying the register setting, the CPU must not access 376 * SDRAM. Luckily for us, we can abuse i-cache here to help us 377 * circumvent the SDRAM access issue. The idea is to make sure 378 * that the code is in one full i-cache line by branching past 379 * it and back. Once it is in the i-cache, we execute the core 380 * of the code and apply the register settings. 381 * 382 * The code below uses 7 instructions, while the Cortex-A9 has 383 * 32-byte cachelines, thus the limit is 8 instructions total. 384 */ 385 asm volatile( 386 ".align 5 \n" 387 " b 2f \n" 388 "1: str %0, [%1] \n" 389 " dsb \n" 390 " isb \n" 391 " b 3f \n" 392 "2: b 1b \n" 393 "3: nop \n" 394 : : "r"(val), "r"(staticcfg) : "memory", "cc"); 395 } 396 397 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 398 { 399 if (argc != 2) 400 return CMD_RET_USAGE; 401 402 argv++; 403 404 switch (*argv[0]) { 405 case 'e': /* Enable */ 406 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); 407 socfpga_sdram_apply_static_cfg(); 408 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); 409 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); 410 writel(iswgrp_handoff[1], &nic301_regs->remap); 411 break; 412 case 'd': /* Disable */ 413 writel(0, &sysmgr_regs->fpgaintfgrp_module); 414 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); 415 socfpga_sdram_apply_static_cfg(); 416 writel(0, &reset_manager_base->brg_mod_reset); 417 writel(1, &nic301_regs->remap); 418 break; 419 default: 420 return CMD_RET_USAGE; 421 } 422 423 return 0; 424 } 425 426 U_BOOT_CMD( 427 bridge, 2, 1, do_bridge, 428 "SoCFPGA HPS FPGA bridge control", 429 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 430 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 431 "" 432 ); 433