1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <altera.h> 12 #include <miiphy.h> 13 #include <netdev.h> 14 #include <watchdog.h> 15 #include <asm/arch/misc.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/scan_manager.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/nic301.h> 20 #include <asm/arch/scu.h> 21 #include <asm/pl310.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef CONFIG_SYS_L2_PL310 26 static const struct pl310_regs *const pl310 = 27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 28 #endif 29 30 struct bsel bsel_str[] = { 31 { "rsvd", "Reserved", }, 32 { "fpga", "FPGA (HPS2FPGA Bridge)", }, 33 { "nand", "NAND Flash (1.8V)", }, 34 { "nand", "NAND Flash (3.0V)", }, 35 { "sd", "SD/MMC External Transceiver (1.8V)", }, 36 { "sd", "SD/MMC Internal Transceiver (3.0V)", }, 37 { "qspi", "QSPI Flash (1.8V)", }, 38 { "qspi", "QSPI Flash (3.0V)", }, 39 }; 40 41 int dram_init(void) 42 { 43 if (fdtdec_setup_mem_size_base() != 0) 44 return -EINVAL; 45 46 return 0; 47 } 48 49 void enable_caches(void) 50 { 51 #ifndef CONFIG_SYS_ICACHE_OFF 52 icache_enable(); 53 #endif 54 #ifndef CONFIG_SYS_DCACHE_OFF 55 dcache_enable(); 56 #endif 57 } 58 59 #ifdef CONFIG_SYS_L2_PL310 60 void v7_outer_cache_enable(void) 61 { 62 /* Disable the L2 cache */ 63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 64 65 /* enable BRESP, instruction and data prefetch, full line of zeroes */ 66 setbits_le32(&pl310->pl310_aux_ctrl, 67 L310_AUX_CTRL_DATA_PREFETCH_MASK | 68 L310_AUX_CTRL_INST_PREFETCH_MASK | 69 L310_SHARED_ATT_OVERRIDE_ENABLE); 70 71 /* Enable the L2 cache */ 72 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 73 } 74 75 void v7_outer_cache_disable(void) 76 { 77 /* Disable the L2 cache */ 78 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 79 } 80 #endif 81 82 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 83 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 84 int overwrite_console(void) 85 { 86 return 0; 87 } 88 #endif 89 90 #ifdef CONFIG_FPGA 91 /* add device descriptor to FPGA device table */ 92 void socfpga_fpga_add(void *fpga_desc) 93 { 94 fpga_init(); 95 fpga_add(fpga_altera, fpga_desc); 96 } 97 #endif 98 99 int arch_cpu_init(void) 100 { 101 #ifdef CONFIG_HW_WATCHDOG 102 /* 103 * In case the watchdog is enabled, make sure to (re-)configure it 104 * so that the defined timeout is valid. Otherwise the SPL (Perloader) 105 * timeout value is still active which might too short for Linux 106 * booting. 107 */ 108 hw_watchdog_init(); 109 #else 110 /* 111 * If the HW watchdog is NOT enabled, make sure it is not running, 112 * for example because it was enabled in the preloader. This might 113 * trigger a watchdog-triggered reboot of Linux kernel later. 114 * Toggle watchdog reset, so watchdog in not running state. 115 */ 116 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); 117 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); 118 #endif 119 120 return 0; 121 } 122 123 #ifdef CONFIG_ETH_DESIGNWARE 124 static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) 125 { 126 if (!phymode) 127 return -EINVAL; 128 129 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { 130 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 131 return 0; 132 } 133 134 if (!strcmp(phymode, "rgmii")) { 135 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 136 return 0; 137 } 138 139 if (!strcmp(phymode, "rmii")) { 140 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; 141 return 0; 142 } 143 144 return -EINVAL; 145 } 146 147 int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, 148 const u8 phymode)) 149 { 150 const void *fdt = gd->fdt_blob; 151 struct fdtdec_phandle_args args; 152 const char *phy_mode; 153 u32 phy_modereg; 154 int nodes[2]; /* Max. two GMACs */ 155 int ret, count; 156 int i, node; 157 158 count = fdtdec_find_aliases_for_id(fdt, "ethernet", 159 COMPAT_ALTERA_SOCFPGA_DWMAC, 160 nodes, ARRAY_SIZE(nodes)); 161 for (i = 0; i < count; i++) { 162 node = nodes[i]; 163 if (node <= 0) 164 continue; 165 166 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", 167 "#reset-cells", 1, 0, 168 &args); 169 if (ret || (args.args_count != 1)) { 170 debug("GMAC%i: Failed to parse DT 'resets'!\n", i); 171 continue; 172 } 173 174 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); 175 ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); 176 if (ret) { 177 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); 178 continue; 179 } 180 181 resetfn(args.args[0], phy_modereg); 182 } 183 184 return 0; 185 } 186 #endif 187 188 #ifndef CONFIG_SPL_BUILD 189 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 190 { 191 if (argc != 2) 192 return CMD_RET_USAGE; 193 194 argv++; 195 196 switch (*argv[0]) { 197 case 'e': /* Enable */ 198 do_bridge_reset(1); 199 break; 200 case 'd': /* Disable */ 201 do_bridge_reset(0); 202 break; 203 default: 204 return CMD_RET_USAGE; 205 } 206 207 return 0; 208 } 209 210 U_BOOT_CMD(bridge, 2, 1, do_bridge, 211 "SoCFPGA HPS FPGA bridge control", 212 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 213 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" 214 "" 215 ); 216 217 #endif 218