1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #ifndef	_SYSTEM_MANAGER_S10_
8 #define	_SYSTEM_MANAGER_S10_
9 
10 void sysmgr_pinmux_init(void);
11 void populate_sysmgr_fpgaintf_module(void);
12 void populate_sysmgr_pinmux(void);
13 void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
14 void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
15 void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
16 void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
17 
18 struct socfpga_system_manager {
19 	/* System Manager Module */
20 	u32	siliconid1;			/* 0x00 */
21 	u32	siliconid2;
22 	u32	wddbg;
23 	u32	_pad_0xc;
24 	u32	mpu_status;			/* 0x10 */
25 	u32	mpu_ace;
26 	u32	_pad_0x18_0x1c[2];
27 	u32	dma;				/* 0x20 */
28 	u32	dma_periph;
29 	/* SDMMC Controller Group */
30 	u32	sdmmcgrp_ctrl;
31 	u32	sdmmcgrp_l3master;
32 	/* NAND Flash Controller Register Group */
33 	u32	nandgrp_bootstrap;		/* 0x30 */
34 	u32	nandgrp_l3master;
35 	/* USB Controller Group */
36 	u32	usb0_l3master;
37 	u32	usb1_l3master;
38 	/* EMAC Group */
39 	u32	emac_gbl;			/* 0x40 */
40 	u32	emac0;
41 	u32	emac1;
42 	u32	emac2;
43 	u32	emac0_ace;			/* 0x50 */
44 	u32	emac1_ace;
45 	u32	emac2_ace;
46 	u32	nand_axuser;
47 	u32	_pad_0x60_0x64[2];		/* 0x60 */
48 	/* FPGA interface Group */
49 	u32	fpgaintf_en_1;
50 	u32	fpgaintf_en_2;
51 	u32	fpgaintf_en_3;			/* 0x70 */
52 	u32	dma_l3master;
53 	u32	etr_l3master;
54 	u32	_pad_0x7c;
55 	u32	sec_ctrl_slt;			/* 0x80 */
56 	u32	osc_trim;
57 	u32	_pad_0x88_0x8c[2];
58 	/* ECC Group */
59 	u32	ecc_intmask_value;		/* 0x90 */
60 	u32	ecc_intmask_set;
61 	u32	ecc_intmask_clr;
62 	u32	ecc_intstatus_serr;
63 	u32	ecc_intstatus_derr;		/* 0xa0 */
64 	u32	_pad_0xa4_0xac[3];
65 	u32	noc_addr_remap;			/* 0xb0 */
66 	u32	hmc_clk;
67 	u32	io_pa_ctrl;
68 	u32	_pad_0xbc;
69 	/* NOC Group */
70 	u32	noc_timeout;			/* 0xc0 */
71 	u32	noc_idlereq_set;
72 	u32	noc_idlereq_clr;
73 	u32	noc_idlereq_value;
74 	u32	noc_idleack;			/* 0xd0 */
75 	u32	noc_idlestatus;
76 	u32	fpga2soc_ctrl;
77 	u32	fpga_config;
78 	u32	iocsrclk_gate;			/* 0xe0 */
79 	u32	gpo;
80 	u32	gpi;
81 	u32	_pad_0xec;
82 	u32	mpu;				/* 0xf0 */
83 	u32	sdm_hps_spare;
84 	u32	hps_sdm_spare;
85 	u32	_pad_0xfc_0x1fc[65];
86 	/* Boot scratch register group */
87 	u32	boot_scratch_cold0;		/* 0x200 */
88 	u32	boot_scratch_cold1;
89 	u32	boot_scratch_cold2;
90 	u32	boot_scratch_cold3;
91 	u32	boot_scratch_cold4;		/* 0x210 */
92 	u32	boot_scratch_cold5;
93 	u32	boot_scratch_cold6;
94 	u32	boot_scratch_cold7;
95 	u32	boot_scratch_cold8;		/* 0x220 */
96 	u32	boot_scratch_cold9;
97 	u32	_pad_0x228_0xffc[886];
98 	/* Pin select and pin control group */
99 	u32	pinsel0[40];			/* 0x1000 */
100 	u32	_pad_0x10a0_0x10fc[24];
101 	u32	pinsel40[8];
102 	u32	_pad_0x1120_0x112c[4];
103 	u32	ioctrl0[28];
104 	u32	_pad_0x11a0_0x11fc[24];
105 	u32	ioctrl28[20];
106 	u32	_pad_0x1250_0x12fc[44];
107 	/* Use FPGA mux */
108 	u32	rgmii0usefpga;			/* 0x1300 */
109 	u32	rgmii1usefpga;
110 	u32	rgmii2usefpga;
111 	u32	i2c0usefpga;
112 	u32	i2c1usefpga;
113 	u32	i2c_emac0_usefpga;
114 	u32	i2c_emac1_usefpga;
115 	u32	i2c_emac2_usefpga;
116 	u32	nandusefpga;
117 	u32	_pad_0x1324;
118 	u32	spim0usefpga;
119 	u32	spim1usefpga;
120 	u32	spis0usefpga;
121 	u32	spis1usefpga;
122 	u32	uart0usefpga;
123 	u32	uart1usefpga;
124 	u32	mdio0usefpga;
125 	u32	mdio1usefpga;
126 	u32	mdio2usefpga;
127 	u32	_pad_0x134c;
128 	u32	jtagusefpga;
129 	u32	sdmmcusefpga;
130 	u32	hps_osc_clk;
131 	u32	_pad_0x135c_0x13fc[41];
132 	u32	iodelay0[40];
133 	u32	_pad_0x14a0_0x14fc[24];
134 	u32	iodelay40[8];
135 
136 };
137 
138 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
139 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
140 #define SYSMGR_ECC_OCRAM_EN	BIT(0)
141 #define SYSMGR_ECC_OCRAM_SERR	BIT(3)
142 #define SYSMGR_ECC_OCRAM_DERR	BIT(4)
143 #define SYSMGR_FPGAINTF_USEFPGA	0x1
144 
145 #define SYSMGR_FPGAINTF_NAND	BIT(4)
146 #define SYSMGR_FPGAINTF_SDMMC	BIT(8)
147 #define SYSMGR_FPGAINTF_SPIM0	BIT(16)
148 #define SYSMGR_FPGAINTF_SPIM1	BIT(24)
149 #define SYSMGR_FPGAINTF_EMAC0	(0x11 << 0)
150 #define SYSMGR_FPGAINTF_EMAC1	(0x11 << 8)
151 #define SYSMGR_FPGAINTF_EMAC2	(0x11 << 16)
152 
153 #define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
154 #define SYSMGR_SDMMC_DRVSEL_SHIFT	0
155 
156 /* EMAC Group Bit definitions */
157 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
158 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
159 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
160 
161 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
162 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
163 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
164 
165 #define SYSMGR_NOC_H2F_MSK		0x00000001
166 #define SYSMGR_NOC_LWH2F_MSK		0x00000010
167 #define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
168 
169 #define SYSMGR_DMA_IRQ_NS		0xFF000000
170 #define SYSMGR_DMA_MGR_NS		0x00010000
171 
172 #define SYSMGR_DMAPERIPH_ALL_NS		0xFFFFFFFF
173 
174 #define SYSMGR_WDDBG_PAUSE_ALL_CPU	0x0F0F0F0F
175 
176 #endif /* _SYSTEM_MANAGER_S10_ */
177