1 /* 2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _SYSTEM_MANAGER_GEN5_H_ 8 #define _SYSTEM_MANAGER_GEN5_H_ 9 10 #ifndef __ASSEMBLY__ 11 12 void sysmgr_pinmux_init(void); 13 void sysmgr_config_warmrstcfgio(int enable); 14 15 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); 16 17 struct socfpga_system_manager { 18 /* System Manager Module */ 19 u32 siliconid1; /* 0x00 */ 20 u32 siliconid2; 21 u32 _pad_0x8_0xf[2]; 22 u32 wddbg; /* 0x10 */ 23 u32 bootinfo; 24 u32 hpsinfo; 25 u32 parityinj; 26 /* FPGA Interface Group */ 27 u32 fpgaintfgrp_gbl; /* 0x20 */ 28 u32 fpgaintfgrp_indiv; 29 u32 fpgaintfgrp_module; 30 u32 _pad_0x2c_0x2f; 31 /* Scan Manager Group */ 32 u32 scanmgrgrp_ctrl; /* 0x30 */ 33 u32 _pad_0x34_0x3f[3]; 34 /* Freeze Control Group */ 35 u32 frzctrl_vioctrl; /* 0x40 */ 36 u32 _pad_0x44_0x4f[3]; 37 u32 frzctrl_hioctrl; /* 0x50 */ 38 u32 frzctrl_src; 39 u32 frzctrl_hwctrl; 40 u32 _pad_0x5c_0x5f; 41 /* EMAC Group */ 42 u32 emacgrp_ctrl; /* 0x60 */ 43 u32 emacgrp_l3master; 44 u32 _pad_0x68_0x6f[2]; 45 /* DMA Controller Group */ 46 u32 dmagrp_ctrl; /* 0x70 */ 47 u32 dmagrp_persecurity; 48 u32 _pad_0x78_0x7f[2]; 49 /* Preloader (initial software) Group */ 50 u32 iswgrp_handoff[8]; /* 0x80 */ 51 u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ 52 /* Boot ROM Code Register Group */ 53 u32 romcodegrp_ctrl; /* 0xc0 */ 54 u32 romcodegrp_cpu1startaddr; 55 u32 romcodegrp_initswstate; 56 u32 romcodegrp_initswlastld; 57 u32 romcodegrp_bootromswstate; /* 0xd0 */ 58 u32 __pad_0xd4_0xdf[3]; 59 /* Warm Boot from On-Chip RAM Group */ 60 u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ 61 u32 romcodegrp_warmramgrp_datastart; 62 u32 romcodegrp_warmramgrp_length; 63 u32 romcodegrp_warmramgrp_execution; 64 u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ 65 u32 __pad_0xf4_0xff[3]; 66 /* Boot ROM Hardware Register Group */ 67 u32 romhwgrp_ctrl; /* 0x100 */ 68 u32 _pad_0x104_0x107; 69 /* SDMMC Controller Group */ 70 u32 sdmmcgrp_ctrl; 71 u32 sdmmcgrp_l3master; 72 /* NAND Flash Controller Register Group */ 73 u32 nandgrp_bootstrap; /* 0x110 */ 74 u32 nandgrp_l3master; 75 /* USB Controller Group */ 76 u32 usbgrp_l3master; 77 u32 _pad_0x11c_0x13f[9]; 78 /* ECC Management Register Group */ 79 u32 eccgrp_l2; /* 0x140 */ 80 u32 eccgrp_ocram; 81 u32 eccgrp_usb0; 82 u32 eccgrp_usb1; 83 u32 eccgrp_emac0; /* 0x150 */ 84 u32 eccgrp_emac1; 85 u32 eccgrp_dma; 86 u32 eccgrp_can0; 87 u32 eccgrp_can1; /* 0x160 */ 88 u32 eccgrp_nand; 89 u32 eccgrp_qspi; 90 u32 eccgrp_sdmmc; 91 u32 _pad_0x170_0x3ff[164]; 92 /* Pin Mux Control Group */ 93 u32 emacio[20]; /* 0x400 */ 94 u32 flashio[12]; /* 0x450 */ 95 u32 generalio[28]; /* 0x480 */ 96 u32 _pad_0x4f0_0x4ff[4]; 97 u32 mixed1io[22]; /* 0x500 */ 98 u32 mixed2io[8]; /* 0x558 */ 99 u32 gplinmux[23]; /* 0x578 */ 100 u32 gplmux[71]; /* 0x5d4 */ 101 u32 nandusefpga; /* 0x6f0 */ 102 u32 _pad_0x6f4; 103 u32 rgmii1usefpga; /* 0x6f8 */ 104 u32 _pad_0x6fc_0x700[2]; 105 u32 i2c0usefpga; /* 0x704 */ 106 u32 sdmmcusefpga; /* 0x708 */ 107 u32 _pad_0x70c_0x710[2]; 108 u32 rgmii0usefpga; /* 0x714 */ 109 u32 _pad_0x718_0x720[3]; 110 u32 i2c3usefpga; /* 0x724 */ 111 u32 i2c2usefpga; /* 0x728 */ 112 u32 i2c1usefpga; /* 0x72c */ 113 u32 spim1usefpga; /* 0x730 */ 114 u32 _pad_0x734; 115 u32 spim0usefpga; /* 0x738 */ 116 }; 117 #endif 118 119 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 120 #define SYSMGR_BOOTINFO_BSEL_SHIFT 0 121 122 #endif /* _SYSTEM_MANAGER_GEN5_H_ */ 123