1*86f032e6SLey Foon Tan /* 2*86f032e6SLey Foon Tan * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> 3*86f032e6SLey Foon Tan * 4*86f032e6SLey Foon Tan * SPDX-License-Identifier: GPL-2.0 5*86f032e6SLey Foon Tan */ 6*86f032e6SLey Foon Tan 7*86f032e6SLey Foon Tan #ifndef _SYSTEM_MANAGER_ARRIA10_H_ 8*86f032e6SLey Foon Tan #define _SYSTEM_MANAGER_ARRIA10_H_ 9*86f032e6SLey Foon Tan 10*86f032e6SLey Foon Tan struct socfpga_system_manager { 11*86f032e6SLey Foon Tan u32 siliconid1; 12*86f032e6SLey Foon Tan u32 siliconid2; 13*86f032e6SLey Foon Tan u32 wddbg; 14*86f032e6SLey Foon Tan u32 bootinfo; 15*86f032e6SLey Foon Tan u32 mpu_ctrl_l2_ecc; 16*86f032e6SLey Foon Tan u32 _pad_0x14_0x1f[3]; 17*86f032e6SLey Foon Tan u32 dma; 18*86f032e6SLey Foon Tan u32 dma_periph; 19*86f032e6SLey Foon Tan u32 sdmmcgrp_ctrl; 20*86f032e6SLey Foon Tan u32 sdmmc_l3master; 21*86f032e6SLey Foon Tan u32 nand_bootstrap; 22*86f032e6SLey Foon Tan u32 nand_l3master; 23*86f032e6SLey Foon Tan u32 usb0_l3master; 24*86f032e6SLey Foon Tan u32 usb1_l3master; 25*86f032e6SLey Foon Tan u32 emac_global; 26*86f032e6SLey Foon Tan u32 emac[3]; 27*86f032e6SLey Foon Tan u32 _pad_0x50_0x5f[4]; 28*86f032e6SLey Foon Tan u32 fpgaintf_en_global; 29*86f032e6SLey Foon Tan u32 fpgaintf_en_0; 30*86f032e6SLey Foon Tan u32 fpgaintf_en_1; 31*86f032e6SLey Foon Tan u32 fpgaintf_en_2; 32*86f032e6SLey Foon Tan u32 fpgaintf_en_3; 33*86f032e6SLey Foon Tan u32 _pad_0x74_0x7f[3]; 34*86f032e6SLey Foon Tan u32 noc_addr_remap_value; 35*86f032e6SLey Foon Tan u32 noc_addr_remap_set; 36*86f032e6SLey Foon Tan u32 noc_addr_remap_clear; 37*86f032e6SLey Foon Tan u32 _pad_0x8c_0x8f; 38*86f032e6SLey Foon Tan u32 ecc_intmask_value; 39*86f032e6SLey Foon Tan u32 ecc_intmask_set; 40*86f032e6SLey Foon Tan u32 ecc_intmask_clr; 41*86f032e6SLey Foon Tan u32 ecc_intstatus_serr; 42*86f032e6SLey Foon Tan u32 ecc_intstatus_derr; 43*86f032e6SLey Foon Tan u32 mpu_status_l2_ecc; 44*86f032e6SLey Foon Tan u32 mpu_clear_l2_ecc; 45*86f032e6SLey Foon Tan u32 mpu_status_l1_parity; 46*86f032e6SLey Foon Tan u32 mpu_clear_l1_parity; 47*86f032e6SLey Foon Tan u32 mpu_set_l1_parity; 48*86f032e6SLey Foon Tan u32 _pad_0xb8_0xbf[2]; 49*86f032e6SLey Foon Tan u32 noc_timeout; 50*86f032e6SLey Foon Tan u32 noc_idlereq_set; 51*86f032e6SLey Foon Tan u32 noc_idlereq_clr; 52*86f032e6SLey Foon Tan u32 noc_idlereq_value; 53*86f032e6SLey Foon Tan u32 noc_idleack; 54*86f032e6SLey Foon Tan u32 noc_idlestatus; 55*86f032e6SLey Foon Tan u32 fpga2soc_ctrl; 56*86f032e6SLey Foon Tan u32 _pad_0xdc_0xff[9]; 57*86f032e6SLey Foon Tan u32 tsmc_tsel_0; 58*86f032e6SLey Foon Tan u32 tsmc_tsel_1; 59*86f032e6SLey Foon Tan u32 tsmc_tsel_2; 60*86f032e6SLey Foon Tan u32 tsmc_tsel_3; 61*86f032e6SLey Foon Tan u32 _pad_0x110_0x200[60]; 62*86f032e6SLey Foon Tan u32 romhw_ctrl; 63*86f032e6SLey Foon Tan u32 romcode_ctrl; 64*86f032e6SLey Foon Tan u32 romcode_cpu1startaddr; 65*86f032e6SLey Foon Tan u32 romcode_initswstate; 66*86f032e6SLey Foon Tan u32 romcode_initswlastld; 67*86f032e6SLey Foon Tan u32 _pad_0x214_0x217; 68*86f032e6SLey Foon Tan u32 warmram_enable; 69*86f032e6SLey Foon Tan u32 warmram_datastart; 70*86f032e6SLey Foon Tan u32 warmram_length; 71*86f032e6SLey Foon Tan u32 warmram_execution; 72*86f032e6SLey Foon Tan u32 warmram_crc; 73*86f032e6SLey Foon Tan u32 _pad_0x22c_0x22f; 74*86f032e6SLey Foon Tan u32 isw_handoff[8]; 75*86f032e6SLey Foon Tan u32 romcode_bootromswstate[8]; 76*86f032e6SLey Foon Tan }; 77*86f032e6SLey Foon Tan 78*86f032e6SLey Foon Tan #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 79*86f032e6SLey Foon Tan #define SYSMGR_BOOTINFO_BSEL_SHIFT 12 80*86f032e6SLey Foon Tan 81*86f032e6SLey Foon Tan #endif /* _SYSTEM_MANAGER_ARRIA10_H_ */ 82