1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _SYSTEM_MANAGER_H_ 7 #define _SYSTEM_MANAGER_H_ 8 9 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) 10 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) 11 #define SYSMGR_ECC_OCRAM_EN BIT(0) 12 #define SYSMGR_ECC_OCRAM_SERR BIT(3) 13 #define SYSMGR_ECC_OCRAM_DERR BIT(4) 14 #define SYSMGR_FPGAINTF_USEFPGA 0x1 15 #define SYSMGR_FPGAINTF_SPIM0 BIT(0) 16 #define SYSMGR_FPGAINTF_SPIM1 BIT(1) 17 #define SYSMGR_FPGAINTF_EMAC0 BIT(2) 18 #define SYSMGR_FPGAINTF_EMAC1 BIT(3) 19 #define SYSMGR_FPGAINTF_NAND BIT(4) 20 #define SYSMGR_FPGAINTF_SDMMC BIT(5) 21 22 #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 23 24 /* EMAC Group Bit definitions */ 25 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 26 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 27 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 28 29 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 30 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 32 33 /* For dedicated IO configuration */ 34 /* Voltage select enums */ 35 #define VOLTAGE_SEL_3V 0x0 36 #define VOLTAGE_SEL_1P8V 0x1 37 #define VOLTAGE_SEL_2P5V 0x2 38 39 /* Input buffer enable */ 40 #define INPUT_BUF_DISABLE 0 41 #define INPUT_BUF_1P8V 1 42 #define INPUT_BUF_2P5V3V 2 43 44 /* Weak pull up enable */ 45 #define WK_PU_DISABLE 0 46 #define WK_PU_ENABLE 1 47 48 /* Pull up slew rate control */ 49 #define PU_SLW_RT_SLOW 0 50 #define PU_SLW_RT_FAST 1 51 #define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW 52 53 /* Pull down slew rate control */ 54 #define PD_SLW_RT_SLOW 0 55 #define PD_SLW_RT_FAST 1 56 #define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW 57 58 /* Drive strength control */ 59 #define PU_DRV_STRG_DEFAULT 0x10 60 #define PD_DRV_STRG_DEFAULT 0x10 61 62 /* bit position */ 63 #define PD_DRV_STRG_LSB 0 64 #define PD_SLW_RT_LSB 5 65 #define PU_DRV_STRG_LSB 8 66 #define PU_SLW_RT_LSB 13 67 #define WK_PU_LSB 16 68 #define INPUT_BUF_LSB 17 69 #define BIAS_TRIM_LSB 19 70 #define VOLTAGE_SEL_LSB 0 71 72 #define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0) 73 #define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4) 74 #define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8) 75 #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16) 76 #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20) 77 #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24) 78 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0) 79 80 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) 81 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) 82 83 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 84 #include <asm/arch/system_manager_gen5.h> 85 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 86 #include <asm/arch/system_manager_arria10.h> 87 #endif 88 89 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ 90 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) 91 92 #endif /* _SYSTEM_MANAGER_H_ */ 93