1 /* 2 * Copyright (C) 2013 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _SYSTEM_MANAGER_H_ 8 #define _SYSTEM_MANAGER_H_ 9 10 #ifndef __ASSEMBLY__ 11 12 void sysmgr_pinmux_init(void); 13 void sysmgr_enable_warmrstcfgio(void); 14 15 /* declaration for handoff table type */ 16 extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; 17 18 #endif 19 20 struct socfpga_system_manager { 21 /* System Manager Module */ 22 u32 siliconid1; /* 0x00 */ 23 u32 siliconid2; 24 u32 _pad_0x8_0xf[2]; 25 u32 wddbg; /* 0x10 */ 26 u32 bootinfo; 27 u32 hpsinfo; 28 u32 parityinj; 29 /* FPGA Interface Group */ 30 u32 fpgaintfgrp_gbl; /* 0x20 */ 31 u32 fpgaintfgrp_indiv; 32 u32 fpgaintfgrp_module; 33 u32 _pad_0x2c_0x2f; 34 /* Scan Manager Group */ 35 u32 scanmgrgrp_ctrl; /* 0x30 */ 36 u32 _pad_0x34_0x3f[3]; 37 /* Freeze Control Group */ 38 u32 frzctrl_vioctrl; /* 0x40 */ 39 u32 _pad_0x44_0x4f[3]; 40 u32 frzctrl_hioctrl; /* 0x50 */ 41 u32 frzctrl_src; 42 u32 frzctrl_hwctrl; 43 u32 _pad_0x5c_0x5f; 44 /* EMAC Group */ 45 u32 emacgrp_ctrl; /* 0x60 */ 46 u32 emacgrp_l3master; 47 u32 _pad_0x68_0x6f[2]; 48 /* DMA Controller Group */ 49 u32 dmagrp_ctrl; /* 0x70 */ 50 u32 dmagrp_persecurity; 51 u32 _pad_0x78_0x7f[2]; 52 /* Preloader (initial software) Group */ 53 u32 iswgrp_handoff[8]; /* 0x80 */ 54 u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ 55 /* Boot ROM Code Register Group */ 56 u32 romcodegrp_ctrl; /* 0xc0 */ 57 u32 romcodegrp_cpu1startaddr; 58 u32 romcodegrp_initswstate; 59 u32 romcodegrp_initswlastld; 60 u32 romcodegrp_bootromswstate; /* 0xd0 */ 61 u32 __pad_0xd4_0xdf[3]; 62 /* Warm Boot from On-Chip RAM Group */ 63 u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ 64 u32 romcodegrp_warmramgrp_datastart; 65 u32 romcodegrp_warmramgrp_length; 66 u32 romcodegrp_warmramgrp_execution; 67 u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ 68 u32 __pad_0xf4_0xff[3]; 69 /* Boot ROM Hardware Register Group */ 70 u32 romhwgrp_ctrl; /* 0x100 */ 71 u32 _pad_0x104_0x107; 72 /* SDMMC Controller Group */ 73 u32 sdmmcgrp_ctrl; 74 u32 sdmmcgrp_l3master; 75 /* NAND Flash Controller Register Group */ 76 u32 nandgrp_bootstrap; /* 0x110 */ 77 u32 nandgrp_l3master; 78 /* USB Controller Group */ 79 u32 usbgrp_l3master; 80 u32 _pad_0x11c_0x13f[9]; 81 /* ECC Management Register Group */ 82 u32 eccgrp_l2; /* 0x140 */ 83 u32 eccgrp_ocram; 84 u32 eccgrp_usb0; 85 u32 eccgrp_usb1; 86 u32 eccgrp_emac0; /* 0x150 */ 87 u32 eccgrp_emac1; 88 u32 eccgrp_dma; 89 u32 eccgrp_can0; 90 u32 eccgrp_can1; /* 0x160 */ 91 u32 eccgrp_nand; 92 u32 eccgrp_qspi; 93 u32 eccgrp_sdmmc; 94 u32 _pad_0x170_0x3ff[164]; 95 /* Pin Mux Control Group */ 96 u32 emacio[20]; /* 0x400 */ 97 u32 flashio[12]; /* 0x450 */ 98 u32 generalio[28]; /* 0x480 */ 99 u32 _pad_0x4f0_0x4ff[4]; 100 u32 mixed1io[22]; /* 0x500 */ 101 u32 mixed2io[8]; /* 0x558 */ 102 u32 gplinmux[23]; /* 0x578 */ 103 u32 gplmux[71]; /* 0x5d4 */ 104 u32 nandusefpga; /* 0x6f0 */ 105 u32 _pad_0x6f4; 106 u32 rgmii1usefpga; /* 0x6f8 */ 107 u32 _pad_0x6fc_0x700[2]; 108 u32 i2c0usefpga; /* 0x704 */ 109 u32 sdmmcusefpga; /* 0x708 */ 110 u32 _pad_0x70c_0x710[2]; 111 u32 rgmii0usefpga; /* 0x714 */ 112 u32 _pad_0x718_0x720[3]; 113 u32 i2c3usefpga; /* 0x724 */ 114 u32 i2c2usefpga; /* 0x728 */ 115 u32 i2c1usefpga; /* 0x72c */ 116 u32 spim1usefpga; /* 0x730 */ 117 u32 _pad_0x734; 118 u32 spim0usefpga; /* 0x738 */ 119 }; 120 121 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) 122 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) 123 #define SYSMGR_ECC_OCRAM_EN (1 << 0) 124 #define SYSMGR_ECC_OCRAM_SERR (1 << 3) 125 #define SYSMGR_ECC_OCRAM_DERR (1 << 4) 126 #define SYSMGR_FPGAINTF_USEFPGA 0x1 127 #define SYSMGR_FPGAINTF_SPIM0 (1 << 0) 128 #define SYSMGR_FPGAINTF_SPIM1 (1 << 1) 129 #define SYSMGR_FPGAINTF_EMAC0 (1 << 2) 130 #define SYSMGR_FPGAINTF_EMAC1 (1 << 3) 131 #define SYSMGR_FPGAINTF_NAND (1 << 4) 132 #define SYSMGR_FPGAINTF_SDMMC (1 << 5) 133 134 /* FIXME: This is questionable macro. */ 135 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ 136 ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) 137 138 /* EMAC Group Bit definitions */ 139 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 140 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 141 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 142 143 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 144 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 145 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 146 147 #endif /* _SYSTEM_MANAGER_H_ */ 148