1 /*
2  * Copyright (C) 2013 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef	_SYSTEM_MANAGER_H_
8 #define	_SYSTEM_MANAGER_H_
9 
10 #ifndef __ASSEMBLY__
11 
12 void sysmgr_pinmux_init(void);
13 void sysmgr_config_warmrstcfgio(int enable);
14 
15 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
16 #endif
17 
18 struct socfpga_system_manager {
19 	/* System Manager Module */
20 	u32	siliconid1;			/* 0x00 */
21 	u32	siliconid2;
22 	u32	_pad_0x8_0xf[2];
23 	u32	wddbg;				/* 0x10 */
24 	u32	bootinfo;
25 	u32	hpsinfo;
26 	u32	parityinj;
27 	/* FPGA Interface Group */
28 	u32	fpgaintfgrp_gbl;		/* 0x20 */
29 	u32	fpgaintfgrp_indiv;
30 	u32	fpgaintfgrp_module;
31 	u32	_pad_0x2c_0x2f;
32 	/* Scan Manager Group */
33 	u32	scanmgrgrp_ctrl;		/* 0x30 */
34 	u32	_pad_0x34_0x3f[3];
35 	/* Freeze Control Group */
36 	u32	frzctrl_vioctrl;		/* 0x40 */
37 	u32	_pad_0x44_0x4f[3];
38 	u32	frzctrl_hioctrl;		/* 0x50 */
39 	u32	frzctrl_src;
40 	u32	frzctrl_hwctrl;
41 	u32	_pad_0x5c_0x5f;
42 	/* EMAC Group */
43 	u32	emacgrp_ctrl;			/* 0x60 */
44 	u32	emacgrp_l3master;
45 	u32	_pad_0x68_0x6f[2];
46 	/* DMA Controller Group */
47 	u32	dmagrp_ctrl;			/* 0x70 */
48 	u32	dmagrp_persecurity;
49 	u32	_pad_0x78_0x7f[2];
50 	/* Preloader (initial software) Group */
51 	u32	iswgrp_handoff[8];		/* 0x80 */
52 	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
53 	/* Boot ROM Code Register Group */
54 	u32	romcodegrp_ctrl;		/* 0xc0 */
55 	u32	romcodegrp_cpu1startaddr;
56 	u32	romcodegrp_initswstate;
57 	u32	romcodegrp_initswlastld;
58 	u32	romcodegrp_bootromswstate;	/* 0xd0 */
59 	u32	__pad_0xd4_0xdf[3];
60 	/* Warm Boot from On-Chip RAM Group */
61 	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
62 	u32	romcodegrp_warmramgrp_datastart;
63 	u32	romcodegrp_warmramgrp_length;
64 	u32	romcodegrp_warmramgrp_execution;
65 	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
66 	u32	__pad_0xf4_0xff[3];
67 	/* Boot ROM Hardware Register Group */
68 	u32	romhwgrp_ctrl;			/* 0x100 */
69 	u32	_pad_0x104_0x107;
70 	/* SDMMC Controller Group */
71 	u32	sdmmcgrp_ctrl;
72 	u32	sdmmcgrp_l3master;
73 	/* NAND Flash Controller Register Group */
74 	u32	nandgrp_bootstrap;		/* 0x110 */
75 	u32	nandgrp_l3master;
76 	/* USB Controller Group */
77 	u32	usbgrp_l3master;
78 	u32	_pad_0x11c_0x13f[9];
79 	/* ECC Management Register Group */
80 	u32	eccgrp_l2;			/* 0x140 */
81 	u32	eccgrp_ocram;
82 	u32	eccgrp_usb0;
83 	u32	eccgrp_usb1;
84 	u32	eccgrp_emac0;			/* 0x150 */
85 	u32	eccgrp_emac1;
86 	u32	eccgrp_dma;
87 	u32	eccgrp_can0;
88 	u32	eccgrp_can1;			/* 0x160 */
89 	u32	eccgrp_nand;
90 	u32	eccgrp_qspi;
91 	u32	eccgrp_sdmmc;
92 	u32	_pad_0x170_0x3ff[164];
93 	/* Pin Mux Control Group */
94 	u32	emacio[20];			/* 0x400 */
95 	u32	flashio[12];			/* 0x450 */
96 	u32	generalio[28];			/* 0x480 */
97 	u32	_pad_0x4f0_0x4ff[4];
98 	u32	mixed1io[22];			/* 0x500 */
99 	u32	mixed2io[8];			/* 0x558 */
100 	u32	gplinmux[23];			/* 0x578 */
101 	u32	gplmux[71];			/* 0x5d4 */
102 	u32	nandusefpga;			/* 0x6f0 */
103 	u32	_pad_0x6f4;
104 	u32	rgmii1usefpga;			/* 0x6f8 */
105 	u32	_pad_0x6fc_0x700[2];
106 	u32	i2c0usefpga;			/* 0x704 */
107 	u32	sdmmcusefpga;			/* 0x708 */
108 	u32	_pad_0x70c_0x710[2];
109 	u32	rgmii0usefpga;			/* 0x714 */
110 	u32	_pad_0x718_0x720[3];
111 	u32	i2c3usefpga;			/* 0x724 */
112 	u32	i2c2usefpga;			/* 0x728 */
113 	u32	i2c1usefpga;			/* 0x72c */
114 	u32	spim1usefpga;			/* 0x730 */
115 	u32	_pad_0x734;
116 	u32	spim0usefpga;			/* 0x738 */
117 };
118 
119 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
120 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
121 #define SYSMGR_ECC_OCRAM_EN	(1 << 0)
122 #define SYSMGR_ECC_OCRAM_SERR	(1 << 3)
123 #define SYSMGR_ECC_OCRAM_DERR	(1 << 4)
124 #define SYSMGR_FPGAINTF_USEFPGA	0x1
125 #define SYSMGR_FPGAINTF_SPIM0	(1 << 0)
126 #define SYSMGR_FPGAINTF_SPIM1	(1 << 1)
127 #define SYSMGR_FPGAINTF_EMAC0	(1 << 2)
128 #define SYSMGR_FPGAINTF_EMAC1	(1 << 3)
129 #define SYSMGR_FPGAINTF_NAND	(1 << 4)
130 #define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
131 
132 /* FIXME: This is questionable macro. */
133 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
134 	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
135 
136 /* EMAC Group Bit definitions */
137 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
138 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
139 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
140 
141 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
142 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
143 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
144 
145 #endif /* _SYSTEM_MANAGER_H_ */
146