1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #ifndef	_SDRAM_S10_H_
8 #define	_SDRAM_S10_H_
9 
10 phys_size_t sdram_calculate_size(void);
11 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
12 int sdram_calibration_full(void);
13 
14 #define DDR_TWR				15
15 #define DDR_READ_LATENCY_DELAY		40
16 #define DDR_ACTIVATE_FAWBANK		0x1
17 
18 /* ECC HMC registers */
19 #define DDRIOCTRL			0x8
20 #define DDRCALSTAT			0xc
21 #define DRAMADDRWIDTH			0xe0
22 #define ECCCTRL1			0x100
23 #define ECCCTRL2			0x104
24 #define ERRINTEN			0x110
25 #define INTMODE				0x11c
26 #define INTSTAT				0x120
27 #define AUTOWB_CORRADDR			0x138
28 #define ECC_REG2WRECCDATABUS		0x144
29 #define ECC_DIAGON			0x150
30 #define ECC_DECSTAT			0x154
31 #define HPSINTFCSEL			0x210
32 #define RSTHANDSHAKECTRL		0x214
33 #define RSTHANDSHAKESTAT		0x218
34 
35 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
36 #define DDR_HMC_DDRCALSTAT_CAL_MSK		BIT(0)
37 #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
38 #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		BIT(8)
39 #define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		BIT(0)
40 #define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
41 #define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
42 #define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	BIT(16)
43 #define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	BIT(0)
44 #define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	BIT(0)
45 #define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	BIT(1)
46 #define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	BIT(0)
47 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
48 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
49 #define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
50 #define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
51 #define DDR_HMC_CORE2SEQ_INT_REQ		0xF
52 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
53 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
54 
55 /* NOC DDR scheduler */
56 #define DDR_SCH_ID_COREID		0
57 #define DDR_SCH_ID_REVID		0x4
58 #define DDR_SCH_DDRCONF			0x8
59 #define DDR_SCH_DDRTIMING		0xc
60 #define DDR_SCH_DDRMODE			0x10
61 #define DDR_SCH_READ_LATENCY		0x14
62 #define DDR_SCH_ACTIVATE		0x38
63 #define DDR_SCH_DEVTODEV		0x3c
64 #define DDR_SCH_DDR4TIMING		0x40
65 
66 #define DDR_SCH_DDRTIMING_ACTTOACT_OFF		0
67 #define DDR_SCH_DDRTIMING_RDTOMISS_OFF		6
68 #define DDR_SCH_DDRTIMING_WRTOMISS_OFF		12
69 #define DDR_SCH_DDRTIMING_BURSTLEN_OFF		18
70 #define DDR_SCH_DDRTIMING_RDTOWR_OFF		21
71 #define DDR_SCH_DDRTIMING_WRTORD_OFF		26
72 #define DDR_SCH_DDRTIMING_BWRATIO_OFF		31
73 #define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF	1
74 #define DDR_SCH_ACTIVATE_RRD_OFF		0
75 #define DDR_SCH_ACTIVATE_FAW_OFF		4
76 #define DDR_SCH_ACTIVATE_FAWBANK_OFF		10
77 #define DDR_SCH_DEVTODEV_BUSRDTORD_OFF		0
78 #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF		2
79 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF		4
80 
81 /* HMC MMR IO48 registers */
82 #define CTRLCFG0			0x28
83 #define CTRLCFG1			0x2c
84 #define DRAMTIMING0			0x50
85 #define CALTIMING0			0x7c
86 #define CALTIMING1			0x80
87 #define CALTIMING2			0x84
88 #define CALTIMING3			0x88
89 #define CALTIMING4			0x8c
90 #define CALTIMING9			0xa0
91 #define DRAMADDRW			0xa8
92 #define DRAMSTS				0xec
93 #define NIOSRESERVED0			0x110
94 #define NIOSRESERVED1			0x114
95 #define NIOSRESERVED2			0x118
96 
97 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
98 	(((x) >> 0) & 0x1F)
99 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
100 	(((x) >> 5) & 0x1F)
101 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
102 	(((x) >> 10) & 0xF)
103 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)		\
104 	(((x) >> 14) & 0x3)
105 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)			\
106 	(((x) >> 16) & 0x7)
107 
108 #define CTRLCFG0_CFG_MEMTYPE(x)				\
109 	(((x) >> 0) & 0xF)
110 #define CTRLCFG0_CFG_DIMM_TYPE(x)			\
111 	(((x) >> 4) & 0x7)
112 #define CTRLCFG0_CFG_AC_POS(x)				\
113 	(((x) >> 7) & 0x3)
114 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x)			\
115 	(((x) >> 9) & 0x1F)
116 
117 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
118 	(((x) >> 0) & 0x1F)
119 #define CTRLCFG1_CFG_ADDR_ORDER(x)			\
120 	(((x) >> 5) & 0x3)
121 #define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
122 	(((x) >> 7) & 0x1)
123 
124 #define DRAMTIMING0_CFG_TCL(x)				\
125 	(((x) >> 0) & 0x7F)
126 
127 #define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
128 	(((x) >> 0) & 0x3F)
129 #define CALTIMING0_CFG_ACT_TO_PCH(x)			\
130 	(((x) >> 6) & 0x3F)
131 #define CALTIMING0_CFG_ACT_TO_ACT(x)			\
132 	(((x) >> 12) & 0x3F)
133 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x)			\
134 	(((x) >> 18) & 0x3F)
135 
136 #define CALTIMING1_CFG_RD_TO_RD(x)			\
137 	(((x) >> 0) & 0x3F)
138 #define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
139 	(((x) >> 6) & 0x3F)
140 #define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
141 	(((x) >> 12) & 0x3F)
142 #define CALTIMING1_CFG_RD_TO_WR(x)			\
143 	(((x) >> 18) & 0x3F)
144 #define CALTIMING1_CFG_RD_TO_WR_DC(x)			\
145 	(((x) >> 24) & 0x3F)
146 
147 #define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
148 	(((x) >> 0) & 0x3F)
149 #define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
150 	(((x) >> 6) & 0x3F)
151 #define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
152 	(((x) >> 12) & 0x3F)
153 #define CALTIMING2_CFG_WR_TO_WR(x)			\
154 	(((x) >> 18) & 0x3F)
155 #define CALTIMING2_CFG_WR_TO_WR_DC(x)			\
156 	(((x) >> 24) & 0x3F)
157 
158 #define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
159 	(((x) >> 0) & 0x3F)
160 #define CALTIMING3_CFG_WR_TO_RD(x)			\
161 	(((x) >> 6) & 0x3F)
162 #define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
163 	(((x) >> 12) & 0x3F)
164 #define CALTIMING3_CFG_WR_TO_RD_DB(x)			\
165 	(((x) >> 18) & 0x3F)
166 #define CALTIMING3_CFG_WR_TO_PCH(x)			\
167 	(((x) >> 24) & 0x3F)
168 
169 #define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
170 	(((x) >> 0) & 0x3F)
171 #define CALTIMING4_CFG_PCH_TO_VALID(x)			\
172 	(((x) >> 6) & 0x3F)
173 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
174 	(((x) >> 12) & 0x3F)
175 #define CALTIMING4_CFG_ARF_TO_VALID(x)			\
176 	(((x) >> 18) & 0xFF)
177 #define CALTIMING4_CFG_PDN_TO_VALID(x)			\
178 	(((x) >> 26) & 0x3F)
179 
180 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
181 	(((x) >> 0) & 0xFF)
182 
183 #endif /* _SDRAM_S10_H_ */
184