1 /* 2 * Copyright Altera Corporation (C) 2014-2015 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _SDRAM_H_ 7 #define _SDRAM_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 unsigned long sdram_calculate_size(void); 12 int sdram_mmr_init_full(unsigned int sdr_phy_reg); 13 int sdram_calibration_full(void); 14 15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void); 16 17 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) 18 19 struct socfpga_sdr_ctrl { 20 u32 ctrl_cfg; 21 u32 dram_timing1; 22 u32 dram_timing2; 23 u32 dram_timing3; 24 u32 dram_timing4; /* 0x10 */ 25 u32 lowpwr_timing; 26 u32 dram_odt; 27 u32 __padding0[4]; 28 u32 dram_addrw; /* 0x2c */ 29 u32 dram_if_width; /* 0x30 */ 30 u32 dram_dev_width; 31 u32 dram_sts; 32 u32 dram_intr; 33 u32 sbe_count; /* 0x40 */ 34 u32 dbe_count; 35 u32 err_addr; 36 u32 drop_count; 37 u32 drop_addr; /* 0x50 */ 38 u32 lowpwr_eq; 39 u32 lowpwr_ack; 40 u32 static_cfg; 41 u32 ctrl_width; /* 0x60 */ 42 u32 cport_width; 43 u32 cport_wmap; 44 u32 cport_rmap; 45 u32 rfifo_cmap; /* 0x70 */ 46 u32 wfifo_cmap; 47 u32 cport_rdwr; 48 u32 port_cfg; 49 u32 fpgaport_rst; /* 0x80 */ 50 u32 __padding1; 51 u32 fifo_cfg; 52 u32 protport_default; 53 u32 prot_rule_addr; /* 0x90 */ 54 u32 prot_rule_id; 55 u32 prot_rule_data; 56 u32 prot_rule_rdwr; 57 u32 __padding2[3]; 58 u32 mp_priority; /* 0xac */ 59 u32 mp_weight0; /* 0xb0 */ 60 u32 mp_weight1; 61 u32 mp_weight2; 62 u32 mp_weight3; 63 u32 mp_pacing0; /* 0xc0 */ 64 u32 mp_pacing1; 65 u32 mp_pacing2; 66 u32 mp_pacing3; 67 u32 mp_threshold0; /* 0xd0 */ 68 u32 mp_threshold1; 69 u32 mp_threshold2; 70 u32 __padding3[29]; 71 u32 phy_ctrl0; /* 0x150 */ 72 u32 phy_ctrl1; 73 u32 phy_ctrl2; 74 }; 75 76 /* SDRAM configuration structure for the SPL. */ 77 struct socfpga_sdram_config { 78 u32 ctrl_cfg; 79 u32 dram_timing1; 80 u32 dram_timing2; 81 u32 dram_timing3; 82 u32 dram_timing4; 83 u32 lowpwr_timing; 84 u32 dram_odt; 85 u32 dram_addrw; 86 u32 dram_if_width; 87 u32 dram_dev_width; 88 u32 dram_intr; 89 u32 lowpwr_eq; 90 u32 static_cfg; 91 u32 ctrl_width; 92 u32 cport_width; 93 u32 cport_wmap; 94 u32 cport_rmap; 95 u32 rfifo_cmap; 96 u32 wfifo_cmap; 97 u32 cport_rdwr; 98 u32 port_cfg; 99 u32 fpgaport_rst; 100 u32 fifo_cfg; 101 u32 mp_priority; 102 u32 mp_weight0; 103 u32 mp_weight1; 104 u32 mp_weight2; 105 u32 mp_weight3; 106 u32 mp_pacing0; 107 u32 mp_pacing1; 108 u32 mp_pacing2; 109 u32 mp_pacing3; 110 u32 mp_threshold0; 111 u32 mp_threshold1; 112 u32 mp_threshold2; 113 u32 phy_ctrl0; 114 }; 115 116 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 117 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 118 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 119 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 120 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 121 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 122 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 123 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 124 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 125 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 126 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 127 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 128 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 129 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 130 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 131 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 132 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 133 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 134 /* Register template: sdr::ctrlgrp::dramtiming1 */ 135 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 136 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 137 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 138 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 139 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 140 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 141 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 142 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 143 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 144 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 145 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 146 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f 147 /* Register template: sdr::ctrlgrp::dramtiming2 */ 148 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 149 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 150 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 151 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 152 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 153 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 154 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 155 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 156 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 157 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff 158 /* Register template: sdr::ctrlgrp::dramtiming3 */ 159 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 160 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 161 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 162 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 163 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 164 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 165 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 166 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 167 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 168 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f 169 /* Register template: sdr::ctrlgrp::dramtiming4 */ 170 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 171 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 172 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 173 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 174 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 175 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff 176 /* Register template: sdr::ctrlgrp::lowpwrtiming */ 177 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 178 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 179 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 180 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff 181 /* Register template: sdr::ctrlgrp::dramaddrw */ 182 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 183 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 184 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 185 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 186 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 187 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 188 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 189 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f 190 /* Register template: sdr::ctrlgrp::dramifwidth */ 191 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 192 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff 193 /* Register template: sdr::ctrlgrp::dramdevwidth */ 194 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 195 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f 196 /* Register template: sdr::ctrlgrp::dramintr */ 197 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 198 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 199 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 200 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 201 /* Register template: sdr::ctrlgrp::staticcfg */ 202 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 203 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 204 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 205 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 206 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 207 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 208 /* Register template: sdr::ctrlgrp::ctrlwidth */ 209 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 210 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 211 /* Register template: sdr::ctrlgrp::cportwidth */ 212 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 213 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff 214 /* Register template: sdr::ctrlgrp::cportwmap */ 215 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 216 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff 217 /* Register template: sdr::ctrlgrp::cportrmap */ 218 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 219 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff 220 /* Register template: sdr::ctrlgrp::rfifocmap */ 221 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 222 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff 223 /* Register template: sdr::ctrlgrp::wfifocmap */ 224 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 225 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff 226 /* Register template: sdr::ctrlgrp::cportrdwr */ 227 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 228 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff 229 /* Register template: sdr::ctrlgrp::portcfg */ 230 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 231 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 232 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 233 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff 234 /* Register template: sdr::ctrlgrp::fifocfg */ 235 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 236 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 237 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 238 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff 239 /* Register template: sdr::ctrlgrp::mppriority */ 240 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 241 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff 242 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ 243 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 244 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff 245 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ 246 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 247 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 248 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 249 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff 250 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ 251 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 252 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff 253 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ 254 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 255 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff 256 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ 257 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 258 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff 259 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ 260 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 261 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 262 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 263 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff 264 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ 265 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 266 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff 267 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ 268 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 269 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff 270 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ 271 #define \ 272 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 273 #define \ 274 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ 275 0xffffffff 276 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ 277 #define \ 278 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 279 #define \ 280 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ 281 0xffffffff 282 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ 283 #define \ 284 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 285 #define \ 286 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ 287 0x0000ffff 288 /* Register template: sdr::ctrlgrp::remappriority */ 289 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 290 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff 291 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ 292 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 293 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 294 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ 295 (((x) << 12) & 0xfffff000) 296 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ 297 (((x) << 10) & 0x00000c00) 298 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ 299 (((x) << 6) & 0x000000c0) 300 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ 301 (((x) << 8) & 0x00000100) 302 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ 303 (((x) << 9) & 0x00000200) 304 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ 305 (((x) << 4) & 0x00000030) 306 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ 307 (((x) << 2) & 0x0000000c) 308 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ 309 (((x) << 0) & 0x00000003) 310 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ 311 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 312 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ 313 (((x) << 12) & 0xfffff000) 314 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ 315 (((x) << 0) & 0x00000fff) 316 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ 317 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ 318 (((x) << 0) & 0x00000fff) 319 /* Register template: sdr::ctrlgrp::dramodt */ 320 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4 321 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 322 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 323 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f 324 /* Field instance: sdr::ctrlgrp::dramsts */ 325 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 326 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 327 328 /* SDRAM width macro for configuration with ECC */ 329 #define SDRAM_WIDTH_32BIT_WITH_ECC 40 330 #define SDRAM_WIDTH_16BIT_WITH_ECC 24 331 332 #endif 333 #endif /* _SDRAM_H_ */ 334