1 /* 2 * Copyright Altera Corporation (C) 2014-2015 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _SDRAM_H_ 7 #define _SDRAM_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 unsigned long sdram_calculate_size(void); 12 int sdram_mmr_init_full(unsigned int sdr_phy_reg); 13 int sdram_calibration_full(void); 14 15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void); 16 17 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); 18 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); 19 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); 20 21 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) 22 23 struct socfpga_sdr_ctrl { 24 u32 ctrl_cfg; 25 u32 dram_timing1; 26 u32 dram_timing2; 27 u32 dram_timing3; 28 u32 dram_timing4; /* 0x10 */ 29 u32 lowpwr_timing; 30 u32 dram_odt; 31 u32 __padding0[4]; 32 u32 dram_addrw; /* 0x2c */ 33 u32 dram_if_width; /* 0x30 */ 34 u32 dram_dev_width; 35 u32 dram_sts; 36 u32 dram_intr; 37 u32 sbe_count; /* 0x40 */ 38 u32 dbe_count; 39 u32 err_addr; 40 u32 drop_count; 41 u32 drop_addr; /* 0x50 */ 42 u32 lowpwr_eq; 43 u32 lowpwr_ack; 44 u32 static_cfg; 45 u32 ctrl_width; /* 0x60 */ 46 u32 cport_width; 47 u32 cport_wmap; 48 u32 cport_rmap; 49 u32 rfifo_cmap; /* 0x70 */ 50 u32 wfifo_cmap; 51 u32 cport_rdwr; 52 u32 port_cfg; 53 u32 fpgaport_rst; /* 0x80 */ 54 u32 __padding1; 55 u32 fifo_cfg; 56 u32 protport_default; 57 u32 prot_rule_addr; /* 0x90 */ 58 u32 prot_rule_id; 59 u32 prot_rule_data; 60 u32 prot_rule_rdwr; 61 u32 __padding2[3]; 62 u32 mp_priority; /* 0xac */ 63 u32 mp_weight0; /* 0xb0 */ 64 u32 mp_weight1; 65 u32 mp_weight2; 66 u32 mp_weight3; 67 u32 mp_pacing0; /* 0xc0 */ 68 u32 mp_pacing1; 69 u32 mp_pacing2; 70 u32 mp_pacing3; 71 u32 mp_threshold0; /* 0xd0 */ 72 u32 mp_threshold1; 73 u32 mp_threshold2; 74 u32 __padding3[29]; 75 u32 phy_ctrl0; /* 0x150 */ 76 u32 phy_ctrl1; 77 u32 phy_ctrl2; 78 }; 79 80 /* SDRAM configuration structure for the SPL. */ 81 struct socfpga_sdram_config { 82 u32 ctrl_cfg; 83 u32 dram_timing1; 84 u32 dram_timing2; 85 u32 dram_timing3; 86 u32 dram_timing4; 87 u32 lowpwr_timing; 88 u32 dram_odt; 89 u32 dram_addrw; 90 u32 dram_if_width; 91 u32 dram_dev_width; 92 u32 dram_intr; 93 u32 lowpwr_eq; 94 u32 static_cfg; 95 u32 ctrl_width; 96 u32 cport_width; 97 u32 cport_wmap; 98 u32 cport_rmap; 99 u32 rfifo_cmap; 100 u32 wfifo_cmap; 101 u32 cport_rdwr; 102 u32 port_cfg; 103 u32 fpgaport_rst; 104 u32 fifo_cfg; 105 u32 mp_priority; 106 u32 mp_weight0; 107 u32 mp_weight1; 108 u32 mp_weight2; 109 u32 mp_weight3; 110 u32 mp_pacing0; 111 u32 mp_pacing1; 112 u32 mp_pacing2; 113 u32 mp_pacing3; 114 u32 mp_threshold0; 115 u32 mp_threshold1; 116 u32 mp_threshold2; 117 u32 phy_ctrl0; 118 }; 119 120 struct socfpga_sdram_rw_mgr_config { 121 u8 activate_0_and_1; 122 u8 activate_0_and_1_wait1; 123 u8 activate_0_and_1_wait2; 124 u8 activate_1; 125 u8 clear_dqs_enable; 126 u8 guaranteed_read; 127 u8 guaranteed_read_cont; 128 u8 guaranteed_write; 129 u8 guaranteed_write_wait0; 130 u8 guaranteed_write_wait1; 131 u8 guaranteed_write_wait2; 132 u8 guaranteed_write_wait3; 133 u8 idle; 134 u8 idle_loop1; 135 u8 idle_loop2; 136 u8 init_reset_0_cke_0; 137 u8 init_reset_1_cke_0; 138 u8 lfsr_wr_rd_bank_0; 139 u8 lfsr_wr_rd_bank_0_data; 140 u8 lfsr_wr_rd_bank_0_dqs; 141 u8 lfsr_wr_rd_bank_0_nop; 142 u8 lfsr_wr_rd_bank_0_wait; 143 u8 lfsr_wr_rd_bank_0_wl_1; 144 u8 lfsr_wr_rd_dm_bank_0; 145 u8 lfsr_wr_rd_dm_bank_0_data; 146 u8 lfsr_wr_rd_dm_bank_0_dqs; 147 u8 lfsr_wr_rd_dm_bank_0_nop; 148 u8 lfsr_wr_rd_dm_bank_0_wait; 149 u8 lfsr_wr_rd_dm_bank_0_wl_1; 150 u8 mrs0_dll_reset; 151 u8 mrs0_dll_reset_mirr; 152 u8 mrs0_user; 153 u8 mrs0_user_mirr; 154 u8 mrs1; 155 u8 mrs1_mirr; 156 u8 mrs2; 157 u8 mrs2_mirr; 158 u8 mrs3; 159 u8 mrs3_mirr; 160 u8 precharge_all; 161 u8 read_b2b; 162 u8 read_b2b_wait1; 163 u8 read_b2b_wait2; 164 u8 refresh_all; 165 u8 rreturn; 166 u8 sgle_read; 167 u8 zqcl; 168 169 u8 true_mem_data_mask_width; 170 u8 mem_address_mirroring; 171 u8 mem_data_mask_width; 172 u8 mem_data_width; 173 u8 mem_dq_per_read_dqs; 174 u8 mem_dq_per_write_dqs; 175 u8 mem_if_read_dqs_width; 176 u8 mem_if_write_dqs_width; 177 u8 mem_number_of_cs_per_dimm; 178 u8 mem_number_of_ranks; 179 u8 mem_virtual_groups_per_read_dqs; 180 u8 mem_virtual_groups_per_write_dqs; 181 }; 182 183 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 184 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 185 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 186 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 187 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 188 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 189 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 190 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 191 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 192 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 193 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 194 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 195 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 196 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 197 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 198 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 199 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 200 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 201 /* Register template: sdr::ctrlgrp::dramtiming1 */ 202 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 203 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 204 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 205 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 206 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 207 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 208 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 209 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 210 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 211 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 212 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 213 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f 214 /* Register template: sdr::ctrlgrp::dramtiming2 */ 215 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 216 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 217 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 218 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 219 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 220 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 221 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 222 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 223 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 224 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff 225 /* Register template: sdr::ctrlgrp::dramtiming3 */ 226 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 227 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 228 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 229 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 230 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 231 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 232 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 233 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 234 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 235 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f 236 /* Register template: sdr::ctrlgrp::dramtiming4 */ 237 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 238 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 239 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 240 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 241 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 242 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff 243 /* Register template: sdr::ctrlgrp::lowpwrtiming */ 244 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 245 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 246 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 247 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff 248 /* Register template: sdr::ctrlgrp::dramaddrw */ 249 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 250 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 251 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 252 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 253 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 254 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 255 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 256 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f 257 /* Register template: sdr::ctrlgrp::dramifwidth */ 258 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 259 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff 260 /* Register template: sdr::ctrlgrp::dramdevwidth */ 261 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 262 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f 263 /* Register template: sdr::ctrlgrp::dramintr */ 264 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 265 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 266 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 267 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 268 /* Register template: sdr::ctrlgrp::staticcfg */ 269 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 270 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 271 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 272 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 273 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 274 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 275 /* Register template: sdr::ctrlgrp::ctrlwidth */ 276 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 277 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 278 /* Register template: sdr::ctrlgrp::cportwidth */ 279 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 280 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff 281 /* Register template: sdr::ctrlgrp::cportwmap */ 282 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 283 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff 284 /* Register template: sdr::ctrlgrp::cportrmap */ 285 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 286 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff 287 /* Register template: sdr::ctrlgrp::rfifocmap */ 288 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 289 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff 290 /* Register template: sdr::ctrlgrp::wfifocmap */ 291 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 292 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff 293 /* Register template: sdr::ctrlgrp::cportrdwr */ 294 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 295 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff 296 /* Register template: sdr::ctrlgrp::portcfg */ 297 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 298 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 299 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 300 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff 301 /* Register template: sdr::ctrlgrp::fifocfg */ 302 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 303 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 304 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 305 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff 306 /* Register template: sdr::ctrlgrp::mppriority */ 307 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 308 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff 309 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ 310 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 311 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff 312 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ 313 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 314 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 315 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 316 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff 317 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ 318 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 319 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff 320 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ 321 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 322 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff 323 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ 324 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 325 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff 326 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ 327 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 328 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 329 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 330 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff 331 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ 332 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 333 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff 334 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ 335 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 336 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff 337 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ 338 #define \ 339 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 340 #define \ 341 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ 342 0xffffffff 343 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ 344 #define \ 345 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 346 #define \ 347 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ 348 0xffffffff 349 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ 350 #define \ 351 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 352 #define \ 353 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ 354 0x0000ffff 355 /* Register template: sdr::ctrlgrp::remappriority */ 356 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 357 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff 358 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ 359 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 360 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 361 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ 362 (((x) << 12) & 0xfffff000) 363 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ 364 (((x) << 10) & 0x00000c00) 365 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ 366 (((x) << 6) & 0x000000c0) 367 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ 368 (((x) << 8) & 0x00000100) 369 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ 370 (((x) << 9) & 0x00000200) 371 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ 372 (((x) << 4) & 0x00000030) 373 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ 374 (((x) << 2) & 0x0000000c) 375 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ 376 (((x) << 0) & 0x00000003) 377 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ 378 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 379 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ 380 (((x) << 12) & 0xfffff000) 381 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ 382 (((x) << 0) & 0x00000fff) 383 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ 384 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ 385 (((x) << 0) & 0x00000fff) 386 /* Register template: sdr::ctrlgrp::dramodt */ 387 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4 388 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 389 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 390 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f 391 /* Field instance: sdr::ctrlgrp::dramsts */ 392 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 393 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 394 395 /* SDRAM width macro for configuration with ECC */ 396 #define SDRAM_WIDTH_32BIT_WITH_ECC 40 397 #define SDRAM_WIDTH_16BIT_WITH_ECC 24 398 399 #endif 400 #endif /* _SDRAM_H_ */ 401