1 /* 2 * Copyright Altera Corporation (C) 2014-2015 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _SDRAM_H_ 7 #define _SDRAM_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 unsigned long sdram_calculate_size(void); 12 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg); 13 int sdram_calibration_full(void); 14 15 extern int sdram_calibration(void); 16 17 #define SDR_CTRLGRP_ADDRESS 0x5000 18 19 struct socfpga_sdr_ctrl { 20 u32 ctrl_cfg; 21 u32 dram_timing1; 22 u32 dram_timing2; 23 u32 dram_timing3; 24 u32 dram_timing4; /* 0x10 */ 25 u32 lowpwr_timing; 26 u32 dram_odt; 27 u32 __padding0[4]; 28 u32 dram_addrw; /* 0x2c */ 29 u32 dram_if_width; /* 0x30 */ 30 u32 dram_dev_width; 31 u32 dram_sts; 32 u32 dram_intr; 33 u32 sbe_count; /* 0x40 */ 34 u32 dbe_count; 35 u32 err_addr; 36 u32 drop_count; 37 u32 drop_addr; /* 0x50 */ 38 u32 lowpwr_eq; 39 u32 lowpwr_ack; 40 u32 static_cfg; 41 u32 ctrl_width; /* 0x60 */ 42 u32 cport_width; 43 u32 cport_wmap; 44 u32 cport_rmap; 45 u32 rfifo_cmap; /* 0x70 */ 46 u32 wfifo_cmap; 47 u32 cport_rdwr; 48 u32 port_cfg; 49 u32 fpgaport_rst; /* 0x80 */ 50 u32 __padding1; 51 u32 fifo_cfg; 52 u32 protport_default; 53 u32 prot_rule_addr; /* 0x90 */ 54 u32 prot_rule_id; 55 u32 prot_rule_data; 56 u32 prot_rule_rdwr; 57 u32 __padding2[3]; 58 u32 mp_priority; /* 0xac */ 59 u32 mp_weight0; /* 0xb0 */ 60 u32 mp_weight1; 61 u32 mp_weight2; 62 u32 mp_weight3; 63 u32 mp_pacing0; /* 0xc0 */ 64 u32 mp_pacing1; 65 u32 mp_pacing2; 66 u32 mp_pacing3; 67 u32 mp_threshold0; /* 0xd0 */ 68 u32 mp_threshold1; 69 u32 mp_threshold2; 70 u32 __padding3[29]; 71 u32 phy_ctrl0; /* 0x150 */ 72 u32 phy_ctrl1; 73 u32 phy_ctrl2; 74 }; 75 76 struct sdram_prot_rule { 77 uint64_t sdram_start; /* SDRAM start address */ 78 uint64_t sdram_end; /* SDRAM end address */ 79 uint32_t rule; /* SDRAM protection rule number: 0-19 */ 80 int valid; /* Rule valid or not? 1 - valid, 0 not*/ 81 82 uint32_t security; 83 uint32_t portmask; 84 uint32_t result; 85 uint32_t lo_prot_id; 86 uint32_t hi_prot_id; 87 }; 88 89 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 90 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 91 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 92 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 93 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 94 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 95 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 96 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 97 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 98 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 99 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 100 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 101 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 102 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 103 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 104 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 105 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 106 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 107 /* Register template: sdr::ctrlgrp::dramtiming1 */ 108 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 109 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 110 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 111 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 112 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 113 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 114 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 115 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 116 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 117 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 118 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 119 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f 120 /* Register template: sdr::ctrlgrp::dramtiming2 */ 121 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 122 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 123 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 124 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 125 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 126 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 127 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 128 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 129 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 130 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff 131 /* Register template: sdr::ctrlgrp::dramtiming3 */ 132 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 133 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 134 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 135 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 136 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 137 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 138 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 139 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 140 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 141 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f 142 /* Register template: sdr::ctrlgrp::dramtiming4 */ 143 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 144 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 145 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 146 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 147 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 148 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff 149 /* Register template: sdr::ctrlgrp::lowpwrtiming */ 150 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 151 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 152 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 153 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff 154 /* Register template: sdr::ctrlgrp::dramaddrw */ 155 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 156 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 157 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 158 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 159 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 160 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 161 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 162 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f 163 /* Register template: sdr::ctrlgrp::dramifwidth */ 164 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 165 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff 166 /* Register template: sdr::ctrlgrp::dramdevwidth */ 167 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 168 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f 169 /* Register template: sdr::ctrlgrp::dramintr */ 170 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 171 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 172 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 173 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 174 /* Register template: sdr::ctrlgrp::staticcfg */ 175 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 176 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 177 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 178 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 179 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 180 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 181 /* Register template: sdr::ctrlgrp::ctrlwidth */ 182 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 183 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 184 /* Register template: sdr::ctrlgrp::cportwidth */ 185 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 186 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff 187 /* Register template: sdr::ctrlgrp::cportwmap */ 188 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 189 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff 190 /* Register template: sdr::ctrlgrp::cportrmap */ 191 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 192 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff 193 /* Register template: sdr::ctrlgrp::rfifocmap */ 194 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 195 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff 196 /* Register template: sdr::ctrlgrp::wfifocmap */ 197 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 198 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff 199 /* Register template: sdr::ctrlgrp::cportrdwr */ 200 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 201 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff 202 /* Register template: sdr::ctrlgrp::portcfg */ 203 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 204 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 205 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 206 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff 207 /* Register template: sdr::ctrlgrp::fifocfg */ 208 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 209 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 210 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 211 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff 212 /* Register template: sdr::ctrlgrp::mppriority */ 213 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 214 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff 215 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ 216 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 217 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff 218 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ 219 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 220 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 221 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 222 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff 223 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ 224 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 225 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff 226 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ 227 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 228 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff 229 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ 230 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 231 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff 232 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ 233 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 234 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 235 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 236 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff 237 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ 238 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 239 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff 240 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ 241 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 242 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff 243 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ 244 #define \ 245 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 246 #define \ 247 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ 248 0xffffffff 249 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ 250 #define \ 251 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 252 #define \ 253 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ 254 0xffffffff 255 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ 256 #define \ 257 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 258 #define \ 259 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ 260 0x0000ffff 261 /* Register template: sdr::ctrlgrp::remappriority */ 262 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 263 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff 264 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ 265 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 266 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 267 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ 268 (((x) << 12) & 0xfffff000) 269 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ 270 (((x) << 10) & 0x00000c00) 271 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ 272 (((x) << 6) & 0x000000c0) 273 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ 274 (((x) << 8) & 0x00000100) 275 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ 276 (((x) << 9) & 0x00000200) 277 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ 278 (((x) << 4) & 0x00000030) 279 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ 280 (((x) << 2) & 0x0000000c) 281 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ 282 (((x) << 0) & 0x00000003) 283 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ 284 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 285 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ 286 (((x) << 12) & 0xfffff000) 287 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ 288 (((x) << 0) & 0x00000fff) 289 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ 290 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ 291 (((x) << 0) & 0x00000fff) 292 /* Register template: sdr::ctrlgrp::dramodt */ 293 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4 294 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 295 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 296 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f 297 /* Field instance: sdr::ctrlgrp::dramsts */ 298 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 299 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 300 301 /* SDRAM width macro for configuration with ECC */ 302 #define SDRAM_WIDTH_32BIT_WITH_ECC 40 303 #define SDRAM_WIDTH_16BIT_WITH_ECC 24 304 305 #endif 306 #endif /* _SDRAM_H_ */ 307