1 /* 2 * Copyright Altera Corporation (C) 2014-2015 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _SDRAM_H_ 7 #define _SDRAM_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 unsigned long sdram_calculate_size(void); 12 int sdram_mmr_init_full(unsigned int sdr_phy_reg); 13 int sdram_calibration_full(void); 14 15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void); 16 17 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); 18 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); 19 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); 20 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void); 21 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void); 22 23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) 24 25 struct socfpga_sdr_ctrl { 26 u32 ctrl_cfg; 27 u32 dram_timing1; 28 u32 dram_timing2; 29 u32 dram_timing3; 30 u32 dram_timing4; /* 0x10 */ 31 u32 lowpwr_timing; 32 u32 dram_odt; 33 u32 extratime1; 34 u32 __padding0[3]; 35 u32 dram_addrw; /* 0x2c */ 36 u32 dram_if_width; /* 0x30 */ 37 u32 dram_dev_width; 38 u32 dram_sts; 39 u32 dram_intr; 40 u32 sbe_count; /* 0x40 */ 41 u32 dbe_count; 42 u32 err_addr; 43 u32 drop_count; 44 u32 drop_addr; /* 0x50 */ 45 u32 lowpwr_eq; 46 u32 lowpwr_ack; 47 u32 static_cfg; 48 u32 ctrl_width; /* 0x60 */ 49 u32 cport_width; 50 u32 cport_wmap; 51 u32 cport_rmap; 52 u32 rfifo_cmap; /* 0x70 */ 53 u32 wfifo_cmap; 54 u32 cport_rdwr; 55 u32 port_cfg; 56 u32 fpgaport_rst; /* 0x80 */ 57 u32 __padding1; 58 u32 fifo_cfg; 59 u32 protport_default; 60 u32 prot_rule_addr; /* 0x90 */ 61 u32 prot_rule_id; 62 u32 prot_rule_data; 63 u32 prot_rule_rdwr; 64 u32 __padding2[3]; 65 u32 mp_priority; /* 0xac */ 66 u32 mp_weight0; /* 0xb0 */ 67 u32 mp_weight1; 68 u32 mp_weight2; 69 u32 mp_weight3; 70 u32 mp_pacing0; /* 0xc0 */ 71 u32 mp_pacing1; 72 u32 mp_pacing2; 73 u32 mp_pacing3; 74 u32 mp_threshold0; /* 0xd0 */ 75 u32 mp_threshold1; 76 u32 mp_threshold2; 77 u32 __padding3[29]; 78 u32 phy_ctrl0; /* 0x150 */ 79 u32 phy_ctrl1; 80 u32 phy_ctrl2; 81 }; 82 83 /* SDRAM configuration structure for the SPL. */ 84 struct socfpga_sdram_config { 85 u32 ctrl_cfg; 86 u32 dram_timing1; 87 u32 dram_timing2; 88 u32 dram_timing3; 89 u32 dram_timing4; 90 u32 lowpwr_timing; 91 u32 dram_odt; 92 u32 extratime1; 93 u32 dram_addrw; 94 u32 dram_if_width; 95 u32 dram_dev_width; 96 u32 dram_intr; 97 u32 lowpwr_eq; 98 u32 static_cfg; 99 u32 ctrl_width; 100 u32 cport_width; 101 u32 cport_wmap; 102 u32 cport_rmap; 103 u32 rfifo_cmap; 104 u32 wfifo_cmap; 105 u32 cport_rdwr; 106 u32 port_cfg; 107 u32 fpgaport_rst; 108 u32 fifo_cfg; 109 u32 mp_priority; 110 u32 mp_weight0; 111 u32 mp_weight1; 112 u32 mp_weight2; 113 u32 mp_weight3; 114 u32 mp_pacing0; 115 u32 mp_pacing1; 116 u32 mp_pacing2; 117 u32 mp_pacing3; 118 u32 mp_threshold0; 119 u32 mp_threshold1; 120 u32 mp_threshold2; 121 u32 phy_ctrl0; 122 }; 123 124 struct socfpga_sdram_rw_mgr_config { 125 u8 activate_0_and_1; 126 u8 activate_0_and_1_wait1; 127 u8 activate_0_and_1_wait2; 128 u8 activate_1; 129 u8 clear_dqs_enable; 130 u8 guaranteed_read; 131 u8 guaranteed_read_cont; 132 u8 guaranteed_write; 133 u8 guaranteed_write_wait0; 134 u8 guaranteed_write_wait1; 135 u8 guaranteed_write_wait2; 136 u8 guaranteed_write_wait3; 137 u8 idle; 138 u8 idle_loop1; 139 u8 idle_loop2; 140 u8 init_reset_0_cke_0; 141 u8 init_reset_1_cke_0; 142 u8 lfsr_wr_rd_bank_0; 143 u8 lfsr_wr_rd_bank_0_data; 144 u8 lfsr_wr_rd_bank_0_dqs; 145 u8 lfsr_wr_rd_bank_0_nop; 146 u8 lfsr_wr_rd_bank_0_wait; 147 u8 lfsr_wr_rd_bank_0_wl_1; 148 u8 lfsr_wr_rd_dm_bank_0; 149 u8 lfsr_wr_rd_dm_bank_0_data; 150 u8 lfsr_wr_rd_dm_bank_0_dqs; 151 u8 lfsr_wr_rd_dm_bank_0_nop; 152 u8 lfsr_wr_rd_dm_bank_0_wait; 153 u8 lfsr_wr_rd_dm_bank_0_wl_1; 154 u8 mrs0_dll_reset; 155 u8 mrs0_dll_reset_mirr; 156 u8 mrs0_user; 157 u8 mrs0_user_mirr; 158 u8 mrs1; 159 u8 mrs1_mirr; 160 u8 mrs2; 161 u8 mrs2_mirr; 162 u8 mrs3; 163 u8 mrs3_mirr; 164 u8 precharge_all; 165 u8 read_b2b; 166 u8 read_b2b_wait1; 167 u8 read_b2b_wait2; 168 u8 refresh_all; 169 u8 rreturn; 170 u8 sgle_read; 171 u8 zqcl; 172 173 u8 true_mem_data_mask_width; 174 u8 mem_address_mirroring; 175 u8 mem_data_mask_width; 176 u8 mem_data_width; 177 u8 mem_dq_per_read_dqs; 178 u8 mem_dq_per_write_dqs; 179 u8 mem_if_read_dqs_width; 180 u8 mem_if_write_dqs_width; 181 u8 mem_number_of_cs_per_dimm; 182 u8 mem_number_of_ranks; 183 u8 mem_virtual_groups_per_read_dqs; 184 u8 mem_virtual_groups_per_write_dqs; 185 }; 186 187 struct socfpga_sdram_io_config { 188 u16 delay_per_opa_tap; 189 u8 delay_per_dchain_tap; 190 u8 delay_per_dqs_en_dchain_tap; 191 u8 dll_chain_length; 192 u8 dqdqs_out_phase_max; 193 u8 dqs_en_delay_max; 194 u8 dqs_en_delay_offset; 195 u8 dqs_en_phase_max; 196 u8 dqs_in_delay_max; 197 u8 dqs_in_reserve; 198 u8 dqs_out_reserve; 199 u8 io_in_delay_max; 200 u8 io_out1_delay_max; 201 u8 io_out2_delay_max; 202 u8 shift_dqs_en_when_shift_dqs; 203 }; 204 205 struct socfpga_sdram_misc_config { 206 u32 reg_file_init_seq_signature; 207 u8 afi_rate_ratio; 208 u8 calib_lfifo_offset; 209 u8 calib_vfifo_offset; 210 u8 enable_super_quick_calibration; 211 u8 max_latency_count_width; 212 u8 read_valid_fifo_size; 213 u8 tinit_cntr0_val; 214 u8 tinit_cntr1_val; 215 u8 tinit_cntr2_val; 216 u8 treset_cntr0_val; 217 u8 treset_cntr1_val; 218 u8 treset_cntr2_val; 219 }; 220 221 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 222 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 223 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 224 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 225 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 226 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 227 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 228 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 229 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 230 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 231 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 232 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 233 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 234 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 235 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 236 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 237 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 238 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 239 /* Register template: sdr::ctrlgrp::dramtiming1 */ 240 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 241 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 242 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 243 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 244 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 245 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 246 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 247 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 248 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 249 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 250 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 251 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f 252 /* Register template: sdr::ctrlgrp::dramtiming2 */ 253 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 254 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 255 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 256 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 257 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 258 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 259 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 260 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 261 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 262 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff 263 /* Register template: sdr::ctrlgrp::dramtiming3 */ 264 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 265 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 266 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 267 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 268 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 269 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 270 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 271 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 272 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 273 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f 274 /* Register template: sdr::ctrlgrp::dramtiming4 */ 275 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 276 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 277 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 278 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 279 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 280 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff 281 /* Register template: sdr::ctrlgrp::lowpwrtiming */ 282 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 283 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 284 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 285 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff 286 /* Register template: sdr::ctrlgrp::dramaddrw */ 287 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 288 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 289 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 290 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 291 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 292 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 293 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 294 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f 295 /* Register template: sdr::ctrlgrp::dramifwidth */ 296 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 297 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff 298 /* Register template: sdr::ctrlgrp::dramdevwidth */ 299 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 300 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f 301 /* Register template: sdr::ctrlgrp::dramintr */ 302 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 303 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 304 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 305 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 306 /* Register template: sdr::ctrlgrp::staticcfg */ 307 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 308 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 309 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 310 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 311 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 312 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 313 /* Register template: sdr::ctrlgrp::ctrlwidth */ 314 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 315 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 316 /* Register template: sdr::ctrlgrp::cportwidth */ 317 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 318 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff 319 /* Register template: sdr::ctrlgrp::cportwmap */ 320 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 321 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff 322 /* Register template: sdr::ctrlgrp::cportrmap */ 323 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 324 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff 325 /* Register template: sdr::ctrlgrp::rfifocmap */ 326 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 327 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff 328 /* Register template: sdr::ctrlgrp::wfifocmap */ 329 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 330 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff 331 /* Register template: sdr::ctrlgrp::cportrdwr */ 332 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 333 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff 334 /* Register template: sdr::ctrlgrp::portcfg */ 335 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 336 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 337 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 338 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff 339 /* Register template: sdr::ctrlgrp::fifocfg */ 340 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 341 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 342 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 343 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff 344 /* Register template: sdr::ctrlgrp::mppriority */ 345 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 346 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff 347 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ 348 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 349 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff 350 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ 351 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 352 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 353 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 354 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff 355 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ 356 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 357 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff 358 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ 359 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 360 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff 361 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ 362 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 363 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff 364 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ 365 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 366 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 367 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 368 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff 369 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ 370 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 371 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff 372 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ 373 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 374 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff 375 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ 376 #define \ 377 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 378 #define \ 379 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ 380 0xffffffff 381 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ 382 #define \ 383 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 384 #define \ 385 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ 386 0xffffffff 387 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ 388 #define \ 389 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 390 #define \ 391 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ 392 0x0000ffff 393 /* Register template: sdr::ctrlgrp::remappriority */ 394 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 395 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff 396 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ 397 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 398 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 399 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ 400 (((x) << 12) & 0xfffff000) 401 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ 402 (((x) << 10) & 0x00000c00) 403 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ 404 (((x) << 6) & 0x000000c0) 405 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ 406 (((x) << 8) & 0x00000100) 407 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ 408 (((x) << 9) & 0x00000200) 409 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ 410 (((x) << 4) & 0x00000030) 411 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ 412 (((x) << 2) & 0x0000000c) 413 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ 414 (((x) << 0) & 0x00000003) 415 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ 416 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 417 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ 418 (((x) << 12) & 0xfffff000) 419 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ 420 (((x) << 0) & 0x00000fff) 421 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ 422 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ 423 (((x) << 0) & 0x00000fff) 424 /* Register template: sdr::ctrlgrp::dramodt */ 425 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4 426 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 427 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 428 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f 429 /* Field instance: sdr::ctrlgrp::dramsts */ 430 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 431 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 432 /* Register template: sdr::ctrlgrp::extratime1 */ 433 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 434 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 435 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 436 437 /* SDRAM width macro for configuration with ECC */ 438 #define SDRAM_WIDTH_32BIT_WITH_ECC 40 439 #define SDRAM_WIDTH_16BIT_WITH_ECC 24 440 441 #endif 442 #endif /* _SDRAM_H_ */ 443