1 /* 2 * Copyright Altera Corporation (C) 2014-2015 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _SDRAM_H_ 7 #define _SDRAM_H_ 8 9 #ifndef __ASSEMBLY__ 10 11 unsigned long sdram_calculate_size(void); 12 int sdram_mmr_init_full(unsigned int sdr_phy_reg); 13 int sdram_calibration_full(void); 14 15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void); 16 17 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); 18 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); 19 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); 20 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void); 21 22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) 23 24 struct socfpga_sdr_ctrl { 25 u32 ctrl_cfg; 26 u32 dram_timing1; 27 u32 dram_timing2; 28 u32 dram_timing3; 29 u32 dram_timing4; /* 0x10 */ 30 u32 lowpwr_timing; 31 u32 dram_odt; 32 u32 __padding0[4]; 33 u32 dram_addrw; /* 0x2c */ 34 u32 dram_if_width; /* 0x30 */ 35 u32 dram_dev_width; 36 u32 dram_sts; 37 u32 dram_intr; 38 u32 sbe_count; /* 0x40 */ 39 u32 dbe_count; 40 u32 err_addr; 41 u32 drop_count; 42 u32 drop_addr; /* 0x50 */ 43 u32 lowpwr_eq; 44 u32 lowpwr_ack; 45 u32 static_cfg; 46 u32 ctrl_width; /* 0x60 */ 47 u32 cport_width; 48 u32 cport_wmap; 49 u32 cport_rmap; 50 u32 rfifo_cmap; /* 0x70 */ 51 u32 wfifo_cmap; 52 u32 cport_rdwr; 53 u32 port_cfg; 54 u32 fpgaport_rst; /* 0x80 */ 55 u32 __padding1; 56 u32 fifo_cfg; 57 u32 protport_default; 58 u32 prot_rule_addr; /* 0x90 */ 59 u32 prot_rule_id; 60 u32 prot_rule_data; 61 u32 prot_rule_rdwr; 62 u32 __padding2[3]; 63 u32 mp_priority; /* 0xac */ 64 u32 mp_weight0; /* 0xb0 */ 65 u32 mp_weight1; 66 u32 mp_weight2; 67 u32 mp_weight3; 68 u32 mp_pacing0; /* 0xc0 */ 69 u32 mp_pacing1; 70 u32 mp_pacing2; 71 u32 mp_pacing3; 72 u32 mp_threshold0; /* 0xd0 */ 73 u32 mp_threshold1; 74 u32 mp_threshold2; 75 u32 __padding3[29]; 76 u32 phy_ctrl0; /* 0x150 */ 77 u32 phy_ctrl1; 78 u32 phy_ctrl2; 79 }; 80 81 /* SDRAM configuration structure for the SPL. */ 82 struct socfpga_sdram_config { 83 u32 ctrl_cfg; 84 u32 dram_timing1; 85 u32 dram_timing2; 86 u32 dram_timing3; 87 u32 dram_timing4; 88 u32 lowpwr_timing; 89 u32 dram_odt; 90 u32 dram_addrw; 91 u32 dram_if_width; 92 u32 dram_dev_width; 93 u32 dram_intr; 94 u32 lowpwr_eq; 95 u32 static_cfg; 96 u32 ctrl_width; 97 u32 cport_width; 98 u32 cport_wmap; 99 u32 cport_rmap; 100 u32 rfifo_cmap; 101 u32 wfifo_cmap; 102 u32 cport_rdwr; 103 u32 port_cfg; 104 u32 fpgaport_rst; 105 u32 fifo_cfg; 106 u32 mp_priority; 107 u32 mp_weight0; 108 u32 mp_weight1; 109 u32 mp_weight2; 110 u32 mp_weight3; 111 u32 mp_pacing0; 112 u32 mp_pacing1; 113 u32 mp_pacing2; 114 u32 mp_pacing3; 115 u32 mp_threshold0; 116 u32 mp_threshold1; 117 u32 mp_threshold2; 118 u32 phy_ctrl0; 119 }; 120 121 struct socfpga_sdram_rw_mgr_config { 122 u8 activate_0_and_1; 123 u8 activate_0_and_1_wait1; 124 u8 activate_0_and_1_wait2; 125 u8 activate_1; 126 u8 clear_dqs_enable; 127 u8 guaranteed_read; 128 u8 guaranteed_read_cont; 129 u8 guaranteed_write; 130 u8 guaranteed_write_wait0; 131 u8 guaranteed_write_wait1; 132 u8 guaranteed_write_wait2; 133 u8 guaranteed_write_wait3; 134 u8 idle; 135 u8 idle_loop1; 136 u8 idle_loop2; 137 u8 init_reset_0_cke_0; 138 u8 init_reset_1_cke_0; 139 u8 lfsr_wr_rd_bank_0; 140 u8 lfsr_wr_rd_bank_0_data; 141 u8 lfsr_wr_rd_bank_0_dqs; 142 u8 lfsr_wr_rd_bank_0_nop; 143 u8 lfsr_wr_rd_bank_0_wait; 144 u8 lfsr_wr_rd_bank_0_wl_1; 145 u8 lfsr_wr_rd_dm_bank_0; 146 u8 lfsr_wr_rd_dm_bank_0_data; 147 u8 lfsr_wr_rd_dm_bank_0_dqs; 148 u8 lfsr_wr_rd_dm_bank_0_nop; 149 u8 lfsr_wr_rd_dm_bank_0_wait; 150 u8 lfsr_wr_rd_dm_bank_0_wl_1; 151 u8 mrs0_dll_reset; 152 u8 mrs0_dll_reset_mirr; 153 u8 mrs0_user; 154 u8 mrs0_user_mirr; 155 u8 mrs1; 156 u8 mrs1_mirr; 157 u8 mrs2; 158 u8 mrs2_mirr; 159 u8 mrs3; 160 u8 mrs3_mirr; 161 u8 precharge_all; 162 u8 read_b2b; 163 u8 read_b2b_wait1; 164 u8 read_b2b_wait2; 165 u8 refresh_all; 166 u8 rreturn; 167 u8 sgle_read; 168 u8 zqcl; 169 170 u8 true_mem_data_mask_width; 171 u8 mem_address_mirroring; 172 u8 mem_data_mask_width; 173 u8 mem_data_width; 174 u8 mem_dq_per_read_dqs; 175 u8 mem_dq_per_write_dqs; 176 u8 mem_if_read_dqs_width; 177 u8 mem_if_write_dqs_width; 178 u8 mem_number_of_cs_per_dimm; 179 u8 mem_number_of_ranks; 180 u8 mem_virtual_groups_per_read_dqs; 181 u8 mem_virtual_groups_per_write_dqs; 182 }; 183 184 struct socfpga_sdram_io_config { 185 u16 delay_per_opa_tap; 186 u8 delay_per_dchain_tap; 187 u8 delay_per_dqs_en_dchain_tap; 188 u8 dll_chain_length; 189 u8 dqdqs_out_phase_max; 190 u8 dqs_en_delay_max; 191 u8 dqs_en_delay_offset; 192 u8 dqs_en_phase_max; 193 u8 dqs_in_delay_max; 194 u8 dqs_in_reserve; 195 u8 dqs_out_reserve; 196 u8 io_in_delay_max; 197 u8 io_out1_delay_max; 198 u8 io_out2_delay_max; 199 u8 shift_dqs_en_when_shift_dqs; 200 }; 201 202 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 203 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 204 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 205 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 206 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 207 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 208 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 209 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 210 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 211 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 212 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 213 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 214 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 215 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 216 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 217 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 218 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 219 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 220 /* Register template: sdr::ctrlgrp::dramtiming1 */ 221 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 222 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 223 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 224 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 225 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 226 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 227 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 228 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 229 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 230 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 231 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 232 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f 233 /* Register template: sdr::ctrlgrp::dramtiming2 */ 234 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 235 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 236 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 237 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 238 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 239 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 240 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 241 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 242 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 243 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff 244 /* Register template: sdr::ctrlgrp::dramtiming3 */ 245 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 246 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 247 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 248 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 249 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 250 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 251 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 252 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 253 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 254 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f 255 /* Register template: sdr::ctrlgrp::dramtiming4 */ 256 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 257 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 258 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 259 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 260 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 261 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff 262 /* Register template: sdr::ctrlgrp::lowpwrtiming */ 263 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 264 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 265 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 266 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff 267 /* Register template: sdr::ctrlgrp::dramaddrw */ 268 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 269 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 270 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 271 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 272 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 273 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 274 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 275 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f 276 /* Register template: sdr::ctrlgrp::dramifwidth */ 277 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 278 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff 279 /* Register template: sdr::ctrlgrp::dramdevwidth */ 280 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 281 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f 282 /* Register template: sdr::ctrlgrp::dramintr */ 283 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 284 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 285 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 286 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 287 /* Register template: sdr::ctrlgrp::staticcfg */ 288 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 289 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 290 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 291 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 292 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 293 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 294 /* Register template: sdr::ctrlgrp::ctrlwidth */ 295 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 296 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 297 /* Register template: sdr::ctrlgrp::cportwidth */ 298 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 299 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff 300 /* Register template: sdr::ctrlgrp::cportwmap */ 301 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 302 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff 303 /* Register template: sdr::ctrlgrp::cportrmap */ 304 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 305 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff 306 /* Register template: sdr::ctrlgrp::rfifocmap */ 307 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 308 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff 309 /* Register template: sdr::ctrlgrp::wfifocmap */ 310 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 311 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff 312 /* Register template: sdr::ctrlgrp::cportrdwr */ 313 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 314 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff 315 /* Register template: sdr::ctrlgrp::portcfg */ 316 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 317 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 318 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 319 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff 320 /* Register template: sdr::ctrlgrp::fifocfg */ 321 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 322 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 323 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 324 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff 325 /* Register template: sdr::ctrlgrp::mppriority */ 326 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 327 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff 328 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ 329 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 330 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff 331 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ 332 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 333 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 334 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 335 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff 336 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ 337 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 338 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff 339 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ 340 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 341 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff 342 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ 343 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 344 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff 345 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ 346 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 347 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 348 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 349 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff 350 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ 351 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 352 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff 353 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ 354 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 355 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff 356 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ 357 #define \ 358 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 359 #define \ 360 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ 361 0xffffffff 362 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ 363 #define \ 364 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 365 #define \ 366 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ 367 0xffffffff 368 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ 369 #define \ 370 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 371 #define \ 372 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ 373 0x0000ffff 374 /* Register template: sdr::ctrlgrp::remappriority */ 375 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 376 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff 377 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ 378 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 379 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 380 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ 381 (((x) << 12) & 0xfffff000) 382 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ 383 (((x) << 10) & 0x00000c00) 384 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ 385 (((x) << 6) & 0x000000c0) 386 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ 387 (((x) << 8) & 0x00000100) 388 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ 389 (((x) << 9) & 0x00000200) 390 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ 391 (((x) << 4) & 0x00000030) 392 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ 393 (((x) << 2) & 0x0000000c) 394 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ 395 (((x) << 0) & 0x00000003) 396 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ 397 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 398 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ 399 (((x) << 12) & 0xfffff000) 400 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ 401 (((x) << 0) & 0x00000fff) 402 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ 403 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ 404 (((x) << 0) & 0x00000fff) 405 /* Register template: sdr::ctrlgrp::dramodt */ 406 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4 407 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 408 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 409 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f 410 /* Field instance: sdr::ctrlgrp::dramsts */ 411 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 412 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 413 414 /* SDRAM width macro for configuration with ECC */ 415 #define SDRAM_WIDTH_32BIT_WITH_ECC 40 416 #define SDRAM_WIDTH_16BIT_WITH_ECC 24 417 418 #endif 419 #endif /* _SDRAM_H_ */ 420