1 /*
2  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _RESET_MANAGER_GEN5_H_
8 #define _RESET_MANAGER_GEN5_H_
9 
10 #include <dt-bindings/reset/altr,rst-mgr.h>
11 
12 void reset_deassert_peripherals_handoff(void);
13 void socfpga_bridges_reset(int enable);
14 
15 struct socfpga_reset_manager {
16 	u32	status;
17 	u32	ctrl;
18 	u32	counts;
19 	u32	padding1;
20 	u32	mpu_mod_reset;
21 	u32	per_mod_reset;
22 	u32	per2_mod_reset;
23 	u32	brg_mod_reset;
24 	u32	misc_mod_reset;
25 	u32	padding2[12];
26 	u32	tstscratch;
27 };
28 
29 /*
30  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
31  * 0 ... mpumodrst
32  * 1 ... permodrst
33  * 2 ... per2modrst
34  * 3 ... brgmodrst
35  * 4 ... miscmodrst
36  */
37 #define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
38 #define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
39 #define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
40 #define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
41 #define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
42 #define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
43 #define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
44 #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
45 #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
46 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
47 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
48 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
49 
50 #endif /* _RESET_MANAGER_GEN5_H_ */
51