1 /*
2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef	_RESET_MANAGER_H_
8 #define	_RESET_MANAGER_H_
9 
10 void reset_cpu(ulong addr);
11 void reset_deassert_peripherals_handoff(void);
12 
13 void socfpga_bridges_reset(int enable);
14 
15 void socfpga_emac_reset(int enable);
16 void socfpga_watchdog_reset(void);
17 void socfpga_spim_enable(void);
18 void socfpga_uart0_enable(void);
19 void socfpga_sdram_enable(void);
20 void socfpga_osc1timer_enable(void);
21 
22 struct socfpga_reset_manager {
23 	u32	status;
24 	u32	ctrl;
25 	u32	counts;
26 	u32	padding1;
27 	u32	mpu_mod_reset;
28 	u32	per_mod_reset;
29 	u32	per2_mod_reset;
30 	u32	brg_mod_reset;
31 };
32 
33 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
34 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
35 #else
36 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
37 #endif
38 
39 #define RSTMGR_PERMODRST_EMAC0_LSB	0
40 #define RSTMGR_PERMODRST_EMAC1_LSB	1
41 #define RSTMGR_PERMODRST_L4WD0_LSB	6
42 #define RSTMGR_PERMODRST_OSC1TIMER0_LSB	8
43 #define RSTMGR_PERMODRST_UART0_LSB	16
44 #define RSTMGR_PERMODRST_SPIM0_LSB	18
45 #define RSTMGR_PERMODRST_SPIM1_LSB	19
46 #define RSTMGR_PERMODRST_SDR_LSB	29
47 
48 #endif /* _RESET_MANAGER_H_ */
49