1 /*
2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef	_RESET_MANAGER_H_
8 #define	_RESET_MANAGER_H_
9 
10 void reset_cpu(ulong addr);
11 void reset_deassert_peripherals_handoff(void);
12 
13 void socfpga_bridges_reset(int enable);
14 
15 void socfpga_per_reset(u32 reset, int set);
16 void socfpga_per_reset_all(void);
17 
18 struct socfpga_reset_manager {
19 	u32	status;
20 	u32	ctrl;
21 	u32	counts;
22 	u32	padding1;
23 	u32	mpu_mod_reset;
24 	u32	per_mod_reset;
25 	u32	per2_mod_reset;
26 	u32	brg_mod_reset;
27 	u32	misc_mod_reset;
28 	u32	padding2[12];
29 	u32	tstscratch;
30 };
31 
32 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
33 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
34 #else
35 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
36 #endif
37 
38 /*
39  * Define a reset identifier, from which a permodrst bank ID
40  * and reset ID can be extracted using the subsequent macros
41  * RSTMGR_RESET() and RSTMGR_BANK().
42  */
43 #define RSTMGR_BANK_OFFSET	8
44 #define RSTMGR_BANK_MASK	0x7
45 #define RSTMGR_RESET_OFFSET	0
46 #define RSTMGR_RESET_MASK	0x1f
47 #define RSTMGR_DEFINE(_bank, _offset)		\
48 	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
49 
50 /* Extract reset ID from the reset identifier. */
51 #define RSTMGR_RESET(_reset)			\
52 	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
53 
54 /* Extract bank ID from the reset identifier. */
55 #define RSTMGR_BANK(_reset)			\
56 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
57 
58 /*
59  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
60  * 0 ... mpumodrst
61  * 1 ... permodrst
62  * 2 ... per2modrst
63  * 3 ... brgmodrst
64  * 4 ... miscmodrst
65  */
66 #define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
67 #define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
68 #define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
69 #define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
70 #define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
71 #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
72 #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
73 #define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
74 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
75 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
76 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
77 
78 /* Create a human-readable reference to SoCFPGA reset. */
79 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
80 
81 #endif /* _RESET_MANAGER_H_ */
82