1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #ifndef _RESET_MANAGER_H_
7 #define _RESET_MANAGER_H_
8 
9 void reset_cpu(ulong addr);
10 
11 void socfpga_per_reset(u32 reset, int set);
12 void socfpga_per_reset_all(void);
13 
14 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
15 
16 /*
17  * Define a reset identifier, from which a permodrst bank ID
18  * and reset ID can be extracted using the subsequent macros
19  * RSTMGR_RESET() and RSTMGR_BANK().
20  */
21 #define RSTMGR_BANK_OFFSET	8
22 #define RSTMGR_BANK_MASK	0x7
23 #define RSTMGR_RESET_OFFSET	0
24 #define RSTMGR_RESET_MASK	0x1f
25 #define RSTMGR_DEFINE(_bank, _offset)		\
26 	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
27 
28 /* Extract reset ID from the reset identifier. */
29 #define RSTMGR_RESET(_reset)			\
30 	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
31 
32 /* Extract bank ID from the reset identifier. */
33 #define RSTMGR_BANK(_reset)			\
34 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
35 
36 /* Create a human-readable reference to SoCFPGA reset. */
37 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
38 
39 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
40 #include <asm/arch/reset_manager_gen5.h>
41 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
42 #include <asm/arch/reset_manager_arria10.h>
43 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
44 #include <asm/arch/reset_manager_s10.h>
45 #endif
46 
47 #endif /* _RESET_MANAGER_H_ */
48