1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _RESET_MANAGER_H_ 7 #define _RESET_MANAGER_H_ 8 9 void reset_cpu(ulong addr); 10 11 void socfpga_per_reset(u32 reset, int set); 12 void socfpga_per_reset_all(void); 13 int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, 14 const u8 phymode)); 15 16 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 17 18 /* 19 * Define a reset identifier, from which a permodrst bank ID 20 * and reset ID can be extracted using the subsequent macros 21 * RSTMGR_RESET() and RSTMGR_BANK(). 22 */ 23 #define RSTMGR_BANK_OFFSET 8 24 #define RSTMGR_BANK_MASK 0x7 25 #define RSTMGR_RESET_OFFSET 0 26 #define RSTMGR_RESET_MASK 0x1f 27 #define RSTMGR_DEFINE(_bank, _offset) \ 28 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 29 30 /* Extract reset ID from the reset identifier. */ 31 #define RSTMGR_RESET(_reset) \ 32 (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 33 34 /* Extract bank ID from the reset identifier. */ 35 #define RSTMGR_BANK(_reset) \ 36 (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 37 38 /* Create a human-readable reference to SoCFPGA reset. */ 39 #define SOCFPGA_RESET(_name) RSTMGR_##_name 40 41 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 42 #include <asm/arch/reset_manager_gen5.h> 43 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 44 #include <asm/arch/reset_manager_arria10.h> 45 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) 46 #include <asm/arch/reset_manager_s10.h> 47 #endif 48 49 #endif /* _RESET_MANAGER_H_ */ 50