130088b09SMasahiro Yamada /* 230088b09SMasahiro Yamada * Copyright (C) 2012 Altera Corporation <www.altera.com> 330088b09SMasahiro Yamada * 430088b09SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 530088b09SMasahiro Yamada */ 630088b09SMasahiro Yamada 730088b09SMasahiro Yamada #ifndef _RESET_MANAGER_H_ 830088b09SMasahiro Yamada #define _RESET_MANAGER_H_ 930088b09SMasahiro Yamada 1030088b09SMasahiro Yamada void reset_cpu(ulong addr); 1130088b09SMasahiro Yamada void reset_deassert_peripherals_handoff(void); 1230088b09SMasahiro Yamada 1330088b09SMasahiro Yamada void socfpga_bridges_reset(int enable); 1430088b09SMasahiro Yamada 1530088b09SMasahiro Yamada void socfpga_emac_reset(int enable); 1630088b09SMasahiro Yamada void socfpga_watchdog_reset(void); 1730088b09SMasahiro Yamada void socfpga_spim_enable(void); 1830088b09SMasahiro Yamada void socfpga_uart0_enable(void); 1930088b09SMasahiro Yamada void socfpga_sdram_enable(void); 2030088b09SMasahiro Yamada void socfpga_osc1timer_enable(void); 2130088b09SMasahiro Yamada 2230088b09SMasahiro Yamada struct socfpga_reset_manager { 2330088b09SMasahiro Yamada u32 status; 2430088b09SMasahiro Yamada u32 ctrl; 2530088b09SMasahiro Yamada u32 counts; 2630088b09SMasahiro Yamada u32 padding1; 2730088b09SMasahiro Yamada u32 mpu_mod_reset; 2830088b09SMasahiro Yamada u32 per_mod_reset; 2930088b09SMasahiro Yamada u32 per2_mod_reset; 3030088b09SMasahiro Yamada u32 brg_mod_reset; 31*8d009e45SMarek Vasut u32 misc_mod_reset; 32*8d009e45SMarek Vasut u32 tstscratch; 3330088b09SMasahiro Yamada }; 3430088b09SMasahiro Yamada 3530088b09SMasahiro Yamada #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 3630088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 3730088b09SMasahiro Yamada #else 3830088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 3930088b09SMasahiro Yamada #endif 4030088b09SMasahiro Yamada 4130088b09SMasahiro Yamada #define RSTMGR_PERMODRST_EMAC0_LSB 0 4230088b09SMasahiro Yamada #define RSTMGR_PERMODRST_EMAC1_LSB 1 4330088b09SMasahiro Yamada #define RSTMGR_PERMODRST_L4WD0_LSB 6 4430088b09SMasahiro Yamada #define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 4530088b09SMasahiro Yamada #define RSTMGR_PERMODRST_UART0_LSB 16 4630088b09SMasahiro Yamada #define RSTMGR_PERMODRST_SPIM0_LSB 18 4730088b09SMasahiro Yamada #define RSTMGR_PERMODRST_SPIM1_LSB 19 4830088b09SMasahiro Yamada #define RSTMGR_PERMODRST_SDR_LSB 29 4930088b09SMasahiro Yamada 5030088b09SMasahiro Yamada #endif /* _RESET_MANAGER_H_ */ 51