1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 230088b09SMasahiro Yamada /* 32b09ea48SLey Foon Tan * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 430088b09SMasahiro Yamada */ 530088b09SMasahiro Yamada 630088b09SMasahiro Yamada #ifndef _RESET_MANAGER_H_ 730088b09SMasahiro Yamada #define _RESET_MANAGER_H_ 830088b09SMasahiro Yamada 930088b09SMasahiro Yamada void reset_cpu(ulong addr); 1030088b09SMasahiro Yamada 11bdfc2ef6SMarek Vasut void socfpga_per_reset(u32 reset, int set); 123191611aSMarek Vasut void socfpga_per_reset_all(void); 13bdfc2ef6SMarek Vasut 1430088b09SMasahiro Yamada #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 1530088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 1630088b09SMasahiro Yamada #else 1730088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 1830088b09SMasahiro Yamada #endif 1930088b09SMasahiro Yamada 201115cd2dSMarek Vasut /* 211115cd2dSMarek Vasut * Define a reset identifier, from which a permodrst bank ID 221115cd2dSMarek Vasut * and reset ID can be extracted using the subsequent macros 231115cd2dSMarek Vasut * RSTMGR_RESET() and RSTMGR_BANK(). 241115cd2dSMarek Vasut */ 251115cd2dSMarek Vasut #define RSTMGR_BANK_OFFSET 8 261115cd2dSMarek Vasut #define RSTMGR_BANK_MASK 0x7 271115cd2dSMarek Vasut #define RSTMGR_RESET_OFFSET 0 281115cd2dSMarek Vasut #define RSTMGR_RESET_MASK 0x1f 291115cd2dSMarek Vasut #define RSTMGR_DEFINE(_bank, _offset) \ 301115cd2dSMarek Vasut ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 311115cd2dSMarek Vasut 321115cd2dSMarek Vasut /* Extract reset ID from the reset identifier. */ 331115cd2dSMarek Vasut #define RSTMGR_RESET(_reset) \ 341115cd2dSMarek Vasut (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 351115cd2dSMarek Vasut 361115cd2dSMarek Vasut /* Extract bank ID from the reset identifier. */ 371115cd2dSMarek Vasut #define RSTMGR_BANK(_reset) \ 381115cd2dSMarek Vasut (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 391115cd2dSMarek Vasut 401115cd2dSMarek Vasut /* Create a human-readable reference to SoCFPGA reset. */ 411115cd2dSMarek Vasut #define SOCFPGA_RESET(_name) RSTMGR_##_name 4230088b09SMasahiro Yamada 432b09ea48SLey Foon Tan #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 442b09ea48SLey Foon Tan #include <asm/arch/reset_manager_gen5.h> 45827e6a7eSLey Foon Tan #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 46827e6a7eSLey Foon Tan #include <asm/arch/reset_manager_arria10.h> 472b09ea48SLey Foon Tan #endif 482b09ea48SLey Foon Tan 4930088b09SMasahiro Yamada #endif /* _RESET_MANAGER_H_ */ 50