130088b09SMasahiro Yamada /* 230088b09SMasahiro Yamada * Copyright (C) 2012 Altera Corporation <www.altera.com> 330088b09SMasahiro Yamada * 430088b09SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 530088b09SMasahiro Yamada */ 630088b09SMasahiro Yamada 730088b09SMasahiro Yamada #ifndef _RESET_MANAGER_H_ 830088b09SMasahiro Yamada #define _RESET_MANAGER_H_ 930088b09SMasahiro Yamada 1030088b09SMasahiro Yamada void reset_cpu(ulong addr); 1130088b09SMasahiro Yamada void reset_deassert_peripherals_handoff(void); 1230088b09SMasahiro Yamada 1330088b09SMasahiro Yamada void socfpga_bridges_reset(int enable); 1430088b09SMasahiro Yamada 15bdfc2ef6SMarek Vasut void socfpga_per_reset(u32 reset, int set); 16*3191611aSMarek Vasut void socfpga_per_reset_all(void); 17bdfc2ef6SMarek Vasut 1830088b09SMasahiro Yamada struct socfpga_reset_manager { 1930088b09SMasahiro Yamada u32 status; 2030088b09SMasahiro Yamada u32 ctrl; 2130088b09SMasahiro Yamada u32 counts; 2230088b09SMasahiro Yamada u32 padding1; 2330088b09SMasahiro Yamada u32 mpu_mod_reset; 2430088b09SMasahiro Yamada u32 per_mod_reset; 2530088b09SMasahiro Yamada u32 per2_mod_reset; 2630088b09SMasahiro Yamada u32 brg_mod_reset; 278d009e45SMarek Vasut u32 misc_mod_reset; 288d009e45SMarek Vasut u32 tstscratch; 2930088b09SMasahiro Yamada }; 3030088b09SMasahiro Yamada 3130088b09SMasahiro Yamada #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 3230088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 3330088b09SMasahiro Yamada #else 3430088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 3530088b09SMasahiro Yamada #endif 3630088b09SMasahiro Yamada 371115cd2dSMarek Vasut /* 381115cd2dSMarek Vasut * Define a reset identifier, from which a permodrst bank ID 391115cd2dSMarek Vasut * and reset ID can be extracted using the subsequent macros 401115cd2dSMarek Vasut * RSTMGR_RESET() and RSTMGR_BANK(). 411115cd2dSMarek Vasut */ 421115cd2dSMarek Vasut #define RSTMGR_BANK_OFFSET 8 431115cd2dSMarek Vasut #define RSTMGR_BANK_MASK 0x7 441115cd2dSMarek Vasut #define RSTMGR_RESET_OFFSET 0 451115cd2dSMarek Vasut #define RSTMGR_RESET_MASK 0x1f 461115cd2dSMarek Vasut #define RSTMGR_DEFINE(_bank, _offset) \ 471115cd2dSMarek Vasut ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 481115cd2dSMarek Vasut 491115cd2dSMarek Vasut /* Extract reset ID from the reset identifier. */ 501115cd2dSMarek Vasut #define RSTMGR_RESET(_reset) \ 511115cd2dSMarek Vasut (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 521115cd2dSMarek Vasut 531115cd2dSMarek Vasut /* Extract bank ID from the reset identifier. */ 541115cd2dSMarek Vasut #define RSTMGR_BANK(_reset) \ 551115cd2dSMarek Vasut (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 561115cd2dSMarek Vasut 571115cd2dSMarek Vasut /* 581115cd2dSMarek Vasut * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 591115cd2dSMarek Vasut * 0 ... mpumodrst 601115cd2dSMarek Vasut * 1 ... permodrst 611115cd2dSMarek Vasut * 2 ... per2modrst 621115cd2dSMarek Vasut * 3 ... brgmodrst 631115cd2dSMarek Vasut * 4 ... miscmodrst 641115cd2dSMarek Vasut */ 651115cd2dSMarek Vasut #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 661115cd2dSMarek Vasut #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 671115cd2dSMarek Vasut #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 681115cd2dSMarek Vasut #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 691115cd2dSMarek Vasut #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 701115cd2dSMarek Vasut #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 711115cd2dSMarek Vasut #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 721115cd2dSMarek Vasut #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 731115cd2dSMarek Vasut 741115cd2dSMarek Vasut /* Create a human-readable reference to SoCFPGA reset. */ 751115cd2dSMarek Vasut #define SOCFPGA_RESET(_name) RSTMGR_##_name 7630088b09SMasahiro Yamada 7730088b09SMasahiro Yamada #endif /* _RESET_MANAGER_H_ */ 78