130088b09SMasahiro Yamada /* 230088b09SMasahiro Yamada * Copyright (C) 2012 Altera Corporation <www.altera.com> 330088b09SMasahiro Yamada * 430088b09SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 530088b09SMasahiro Yamada */ 630088b09SMasahiro Yamada 730088b09SMasahiro Yamada #ifndef _RESET_MANAGER_H_ 830088b09SMasahiro Yamada #define _RESET_MANAGER_H_ 930088b09SMasahiro Yamada 1030088b09SMasahiro Yamada void reset_cpu(ulong addr); 1130088b09SMasahiro Yamada void reset_deassert_peripherals_handoff(void); 1230088b09SMasahiro Yamada 1330088b09SMasahiro Yamada void socfpga_bridges_reset(int enable); 1430088b09SMasahiro Yamada 1530088b09SMasahiro Yamada void socfpga_emac_reset(int enable); 1630088b09SMasahiro Yamada void socfpga_watchdog_reset(void); 1730088b09SMasahiro Yamada void socfpga_spim_enable(void); 1830088b09SMasahiro Yamada void socfpga_uart0_enable(void); 1930088b09SMasahiro Yamada void socfpga_sdram_enable(void); 2030088b09SMasahiro Yamada void socfpga_osc1timer_enable(void); 2130088b09SMasahiro Yamada 2230088b09SMasahiro Yamada struct socfpga_reset_manager { 2330088b09SMasahiro Yamada u32 status; 2430088b09SMasahiro Yamada u32 ctrl; 2530088b09SMasahiro Yamada u32 counts; 2630088b09SMasahiro Yamada u32 padding1; 2730088b09SMasahiro Yamada u32 mpu_mod_reset; 2830088b09SMasahiro Yamada u32 per_mod_reset; 2930088b09SMasahiro Yamada u32 per2_mod_reset; 3030088b09SMasahiro Yamada u32 brg_mod_reset; 318d009e45SMarek Vasut u32 misc_mod_reset; 328d009e45SMarek Vasut u32 tstscratch; 3330088b09SMasahiro Yamada }; 3430088b09SMasahiro Yamada 3530088b09SMasahiro Yamada #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 3630088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 3730088b09SMasahiro Yamada #else 3830088b09SMasahiro Yamada #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 3930088b09SMasahiro Yamada #endif 4030088b09SMasahiro Yamada 41*1115cd2dSMarek Vasut /* 42*1115cd2dSMarek Vasut * Define a reset identifier, from which a permodrst bank ID 43*1115cd2dSMarek Vasut * and reset ID can be extracted using the subsequent macros 44*1115cd2dSMarek Vasut * RSTMGR_RESET() and RSTMGR_BANK(). 45*1115cd2dSMarek Vasut */ 46*1115cd2dSMarek Vasut #define RSTMGR_BANK_OFFSET 8 47*1115cd2dSMarek Vasut #define RSTMGR_BANK_MASK 0x7 48*1115cd2dSMarek Vasut #define RSTMGR_RESET_OFFSET 0 49*1115cd2dSMarek Vasut #define RSTMGR_RESET_MASK 0x1f 50*1115cd2dSMarek Vasut #define RSTMGR_DEFINE(_bank, _offset) \ 51*1115cd2dSMarek Vasut ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 52*1115cd2dSMarek Vasut 53*1115cd2dSMarek Vasut /* Extract reset ID from the reset identifier. */ 54*1115cd2dSMarek Vasut #define RSTMGR_RESET(_reset) \ 55*1115cd2dSMarek Vasut (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 56*1115cd2dSMarek Vasut 57*1115cd2dSMarek Vasut /* Extract bank ID from the reset identifier. */ 58*1115cd2dSMarek Vasut #define RSTMGR_BANK(_reset) \ 59*1115cd2dSMarek Vasut (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 60*1115cd2dSMarek Vasut 61*1115cd2dSMarek Vasut /* 62*1115cd2dSMarek Vasut * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: 63*1115cd2dSMarek Vasut * 0 ... mpumodrst 64*1115cd2dSMarek Vasut * 1 ... permodrst 65*1115cd2dSMarek Vasut * 2 ... per2modrst 66*1115cd2dSMarek Vasut * 3 ... brgmodrst 67*1115cd2dSMarek Vasut * 4 ... miscmodrst 68*1115cd2dSMarek Vasut */ 69*1115cd2dSMarek Vasut #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 70*1115cd2dSMarek Vasut #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 71*1115cd2dSMarek Vasut #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) 72*1115cd2dSMarek Vasut #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) 73*1115cd2dSMarek Vasut #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) 74*1115cd2dSMarek Vasut #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) 75*1115cd2dSMarek Vasut #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) 76*1115cd2dSMarek Vasut #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) 77*1115cd2dSMarek Vasut 78*1115cd2dSMarek Vasut /* Create a human-readable reference to SoCFPGA reset. */ 79*1115cd2dSMarek Vasut #define SOCFPGA_RESET(_name) RSTMGR_##_name 8030088b09SMasahiro Yamada 8130088b09SMasahiro Yamada #endif /* _RESET_MANAGER_H_ */ 82