1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #ifndef _MAILBOX_S10_H_
8 #define _MAILBOX_S10_H_
9 
10 /* user define Uboot ID */
11 #define MBOX_CLIENT_ID_UBOOT	0xB
12 #define MBOX_ID_UBOOT		0x1
13 
14 #define MBOX_CMD_DIRECT	0
15 #define MBOX_CMD_INDIRECT	1
16 
17 #define MBOX_MAX_CMD_INDEX	2047
18 #define MBOX_CMD_BUFFER_SIZE	32
19 #define MBOX_RESP_BUFFER_SIZE	16
20 
21 #define MBOX_HDR_CMD_LSB	0
22 #define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
23 #define MBOX_HDR_I_LSB		11
24 #define MBOX_HDR_I_MSK		BIT(11)
25 #define MBOX_HDR_LEN_LSB	12
26 #define MBOX_HDR_LEN_MSK	0x007FF000
27 #define MBOX_HDR_ID_LSB		24
28 #define MBOX_HDR_ID_MSK		0x0F000000
29 #define MBOX_HDR_CLIENT_LSB	28
30 #define MBOX_HDR_CLIENT_MSK	0xF0000000
31 
32 /* Interrupt flags */
33 #define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
34 #define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
35 #define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
36 #define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
37 				 MBOX_FLAGS_INT_RIE | \
38 				 MBOX_FLAGS_INT_UAE)
39 
40 /* Status */
41 #define MBOX_STATUS_UA_MSK	BIT(8)
42 
43 #define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
44 	((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
45 	(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
46 	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
47 	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
48 	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
49 
50 #define MBOX_RESP_ERR_GET(resp)				\
51 	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
52 #define MBOX_RESP_LEN_GET(resp)			\
53 	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
54 #define MBOX_RESP_ID_GET(resp)				\
55 	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
56 #define MBOX_RESP_CLIENT_GET(resp)			\
57 	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
58 
59 /* Response error list */
60 enum ALT_SDM_MBOX_RESP_CODE {
61 	/* CMD completed successfully, but check resp ARGS for any errors */
62 	MBOX_RESP_STATOK = 0,
63 	/* CMD is incorrectly formatted in some way */
64 	MBOX_RESP_INVALID_COMMAND = 1,
65 	/* BootROM Command code not undesrtood */
66 	MBOX_RESP_UNKNOWN_BR = 2,
67 	/* CMD code not recognized by firmware */
68 	MBOX_RESP_UNKNOWN = 3,
69 	/* Indicates that the device is not configured */
70 	MBOX_RESP_NOT_CONFIGURED = 256,
71 	/* Indicates that the device is busy */
72 	MBOX_RESP_DEVICE_BUSY = 0x1FF,
73 	/* Indicates that there is no valid response available */
74 	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
75 	/* General Error */
76 	MBOX_RESP_ERROR = 0x3FF,
77 };
78 
79 /* Mailbox command list */
80 #define MBOX_RESTART		2
81 #define MBOX_CONFIG_STATUS	4
82 #define MBOX_RECONFIG		6
83 #define MBOX_RECONFIG_MSEL	7
84 #define MBOX_RECONFIG_DATA	8
85 #define MBOX_RECONFIG_STATUS	9
86 #define MBOX_QSPI_OPEN		50
87 #define MBOX_QSPI_CLOSE		51
88 #define MBOX_QSPI_DIRECT	59
89 #define MBOX_REBOOT_HPS		71
90 
91 /* Mailbox registers */
92 #define MBOX_CIN			0	/* command valid offset */
93 #define MBOX_ROUT			4	/* response output offset */
94 #define MBOX_URG			8	/* urgent command */
95 #define MBOX_FLAGS			0x0c	/* interrupt enables */
96 #define MBOX_COUT			0x20	/* command free offset */
97 #define MBOX_RIN			0x24	/* respond valid offset */
98 #define MBOX_STATUS			0x2c	/* mailbox status */
99 #define MBOX_CMD_BUF			0x40	/* circular command buffer */
100 #define MBOX_RESP_BUF			0xc0	/* circular response buffer */
101 #define MBOX_DOORBELL_TO_SDM		0x400	/* Doorbell to SDM */
102 #define MBOX_DOORBELL_FROM_SDM		0x480	/* Doorbell from SDM */
103 
104 /* Status and bit information returned by RECONFIG_STATUS */
105 #define RECONFIG_STATUS_RESPONSE_LEN			6
106 #define RECONFIG_STATUS_STATE				0
107 #define RECONFIG_STATUS_PIN_STATUS			2
108 #define RECONFIG_STATUS_SOFTFUNC_STATUS			3
109 
110 #define MBOX_CFGSTAT_STATE_IDLE				0x00000000
111 #define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
112 #define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
113 #define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
114 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
115 #define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
116 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
117 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
118 #define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
119 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
120 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
121 
122 #define RCF_SOFTFUNC_STATUS_CONF_DONE			BIT(0)
123 #define RCF_SOFTFUNC_STATUS_INIT_DONE			BIT(1)
124 #define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
125 #define RCF_PIN_STATUS_NSTATUS				BIT(31)
126 
127 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
128 		  u32 *resp_buf_len, u32 *resp_buf);
129 int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
130 		       u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
131 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
132 int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
133 int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
134 int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
135 int mbox_init(void);
136 
137 #ifdef CONFIG_CADENCE_QSPI
138 int mbox_qspi_close(void);
139 int mbox_qspi_open(void);
140 #endif
141 
142 int mbox_reset_cold(void);
143 
144 #endif /* _MAILBOX_S10_H_ */
145