1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
4  */
5 
6 #ifndef	_FREEZE_CONTROLLER_H_
7 #define	_FREEZE_CONTROLLER_H_
8 
9 struct socfpga_freeze_controller {
10 	u32	vioctrl;
11 	u32	padding[3];
12 	u32	hioctrl;
13 	u32	src;
14 	u32	hwctrl;
15 };
16 
17 #define FREEZE_CHANNEL_NUM		(4)
18 
19 typedef enum {
20 	FREEZE_CTRL_FROZEN = 0,
21 	FREEZE_CTRL_THAWED = 1
22 } FREEZE_CTRL_CHAN_STATE;
23 
24 #define SYSMGR_FRZCTRL_ADDRESS 0x40
25 #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
26 #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
27 #define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
28 #define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
29 #define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
30 #define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
31 #define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
32 #define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
33 #define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
34 #define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
35 #define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
36 #define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
37 #define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
38 #define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
39 #define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
40 #define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
41 #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
42 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
43 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
44 
45 void sys_mgr_frzctrl_freeze_req(void);
46 void sys_mgr_frzctrl_thaw_req(void);
47 
48 #endif /* _FREEZE_CONTROLLER_H_ */
49