1*30088b09SMasahiro Yamada /*
2*30088b09SMasahiro Yamada  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
3*30088b09SMasahiro Yamada  *
4*30088b09SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
5*30088b09SMasahiro Yamada  */
6*30088b09SMasahiro Yamada 
7*30088b09SMasahiro Yamada #ifndef	_FREEZE_CONTROLLER_H_
8*30088b09SMasahiro Yamada #define	_FREEZE_CONTROLLER_H_
9*30088b09SMasahiro Yamada 
10*30088b09SMasahiro Yamada struct socfpga_freeze_controller {
11*30088b09SMasahiro Yamada 	u32	vioctrl;
12*30088b09SMasahiro Yamada 	u32	padding[3];
13*30088b09SMasahiro Yamada 	u32	hioctrl;
14*30088b09SMasahiro Yamada 	u32	src;
15*30088b09SMasahiro Yamada 	u32	hwctrl;
16*30088b09SMasahiro Yamada };
17*30088b09SMasahiro Yamada 
18*30088b09SMasahiro Yamada #define FREEZE_CHANNEL_NUM		(4)
19*30088b09SMasahiro Yamada 
20*30088b09SMasahiro Yamada typedef enum {
21*30088b09SMasahiro Yamada 	FREEZE_CTRL_FROZEN = 0,
22*30088b09SMasahiro Yamada 	FREEZE_CTRL_THAWED = 1
23*30088b09SMasahiro Yamada } FREEZE_CTRL_CHAN_STATE;
24*30088b09SMasahiro Yamada 
25*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_ADDRESS 0x40
26*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
27*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
28*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
29*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
30*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
31*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
32*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
33*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
34*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
35*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
36*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
37*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
38*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
39*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
40*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
41*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
42*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
43*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
44*30088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
45*30088b09SMasahiro Yamada 
46*30088b09SMasahiro Yamada void sys_mgr_frzctrl_freeze_req(void);
47*30088b09SMasahiro Yamada void sys_mgr_frzctrl_thaw_req(void);
48*30088b09SMasahiro Yamada 
49*30088b09SMasahiro Yamada #endif /* _FREEZE_CONTROLLER_H_ */
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