1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 230088b09SMasahiro Yamada /* 330088b09SMasahiro Yamada * Copyright (C) 2013 Altera Corporation <www.altera.com> 430088b09SMasahiro Yamada */ 530088b09SMasahiro Yamada 630088b09SMasahiro Yamada #ifndef _FREEZE_CONTROLLER_H_ 730088b09SMasahiro Yamada #define _FREEZE_CONTROLLER_H_ 830088b09SMasahiro Yamada 930088b09SMasahiro Yamada struct socfpga_freeze_controller { 1030088b09SMasahiro Yamada u32 vioctrl; 1130088b09SMasahiro Yamada u32 padding[3]; 1230088b09SMasahiro Yamada u32 hioctrl; 1330088b09SMasahiro Yamada u32 src; 1430088b09SMasahiro Yamada u32 hwctrl; 1530088b09SMasahiro Yamada }; 1630088b09SMasahiro Yamada 1730088b09SMasahiro Yamada #define FREEZE_CHANNEL_NUM (4) 1830088b09SMasahiro Yamada 1930088b09SMasahiro Yamada typedef enum { 2030088b09SMasahiro Yamada FREEZE_CTRL_FROZEN = 0, 2130088b09SMasahiro Yamada FREEZE_CTRL_THAWED = 1 2230088b09SMasahiro Yamada } FREEZE_CTRL_CHAN_STATE; 2330088b09SMasahiro Yamada 2430088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_ADDRESS 0x40 2530088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 2630088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 2730088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 2830088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 2930088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 3030088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 3130088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 3230088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 3330088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 3430088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 3530088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 3630088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 3730088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 3830088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 3930088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 4030088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 4130088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 4230088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 4330088b09SMasahiro Yamada #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 4430088b09SMasahiro Yamada 4530088b09SMasahiro Yamada void sys_mgr_frzctrl_freeze_req(void); 4630088b09SMasahiro Yamada void sys_mgr_frzctrl_thaw_req(void); 4730088b09SMasahiro Yamada 4830088b09SMasahiro Yamada #endif /* _FREEZE_CONTROLLER_H_ */ 49