1*2baa9972STien Fong Chee /* 2*2baa9972STien Fong Chee * Copyright (C) 2017 Intel Corporation <www.intel.com> 3*2baa9972STien Fong Chee * All rights reserved. 4*2baa9972STien Fong Chee * 5*2baa9972STien Fong Chee * SPDX-License-Identifier: GPL-2.0 6*2baa9972STien Fong Chee */ 7*2baa9972STien Fong Chee 8*2baa9972STien Fong Chee #ifndef _FPGA_MANAGER_ARRIA10_H_ 9*2baa9972STien Fong Chee #define _FPGA_MANAGER_ARRIA10_H_ 10*2baa9972STien Fong Chee 11*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) 12*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) 13*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) 14*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) 15*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) 16*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) 17*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) 18*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) 19*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) 20*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) 21*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) 22*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) 23*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) 24*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) 25*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) 26*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) 27*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) 28*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ 29*2baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ 30*2baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ 31*2baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) 32*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) 33*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) 34*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) 35*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) 36*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 37*2baa9972STien Fong Chee 38*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) 39*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) 40*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) 41*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) 42*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) 43*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) 44*2baa9972STien Fong Chee 45*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) 46*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) 47*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) 48*2baa9972STien Fong Chee 49*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) 50*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) 51*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 52*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) 53*2baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 54*2baa9972STien Fong Chee 55*2baa9972STien Fong Chee #ifndef __ASSEMBLY__ 56*2baa9972STien Fong Chee 57*2baa9972STien Fong Chee struct socfpga_fpga_manager { 58*2baa9972STien Fong Chee u32 _pad_0x0_0x7[2]; 59*2baa9972STien Fong Chee u32 dclkcnt; 60*2baa9972STien Fong Chee u32 dclkstat; 61*2baa9972STien Fong Chee u32 gpo; 62*2baa9972STien Fong Chee u32 gpi; 63*2baa9972STien Fong Chee u32 misci; 64*2baa9972STien Fong Chee u32 _pad_0x1c_0x2f[5]; 65*2baa9972STien Fong Chee u32 emr_data0; 66*2baa9972STien Fong Chee u32 emr_data1; 67*2baa9972STien Fong Chee u32 emr_data2; 68*2baa9972STien Fong Chee u32 emr_data3; 69*2baa9972STien Fong Chee u32 emr_data4; 70*2baa9972STien Fong Chee u32 emr_data5; 71*2baa9972STien Fong Chee u32 emr_valid; 72*2baa9972STien Fong Chee u32 emr_en; 73*2baa9972STien Fong Chee u32 jtag_config; 74*2baa9972STien Fong Chee u32 jtag_status; 75*2baa9972STien Fong Chee u32 jtag_kick; 76*2baa9972STien Fong Chee u32 _pad_0x5c_0x5f; 77*2baa9972STien Fong Chee u32 jtag_data_w; 78*2baa9972STien Fong Chee u32 jtag_data_r; 79*2baa9972STien Fong Chee u32 _pad_0x68_0x6f[2]; 80*2baa9972STien Fong Chee u32 imgcfg_ctrl_00; 81*2baa9972STien Fong Chee u32 imgcfg_ctrl_01; 82*2baa9972STien Fong Chee u32 imgcfg_ctrl_02; 83*2baa9972STien Fong Chee u32 _pad_0x7c_0x7f; 84*2baa9972STien Fong Chee u32 imgcfg_stat; 85*2baa9972STien Fong Chee u32 intr_masked_status; 86*2baa9972STien Fong Chee u32 intr_mask; 87*2baa9972STien Fong Chee u32 intr_polarity; 88*2baa9972STien Fong Chee u32 dma_config; 89*2baa9972STien Fong Chee u32 imgcfg_fifo_status; 90*2baa9972STien Fong Chee }; 91*2baa9972STien Fong Chee 92*2baa9972STien Fong Chee /* Functions */ 93*2baa9972STien Fong Chee int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); 94*2baa9972STien Fong Chee int fpgamgr_program_finish(void); 95*2baa9972STien Fong Chee int is_fpgamgr_user_mode(void); 96*2baa9972STien Fong Chee int fpgamgr_wait_early_user_mode(void); 97*2baa9972STien Fong Chee 98*2baa9972STien Fong Chee #endif /* __ASSEMBLY__ */ 99*2baa9972STien Fong Chee 100*2baa9972STien Fong Chee #endif /* _FPGA_MANAGER_ARRIA10_H_ */ 101