1 /* 2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CLOCK_MANAGER_GEN5_H_ 8 #define _CLOCK_MANAGER_GEN5_H_ 9 10 #ifndef __ASSEMBLER__ 11 12 struct cm_config { 13 /* main group */ 14 u32 main_vco_base; 15 u32 mpuclk; 16 u32 mainclk; 17 u32 dbgatclk; 18 u32 mainqspiclk; 19 u32 mainnandsdmmcclk; 20 u32 cfg2fuser0clk; 21 u32 maindiv; 22 u32 dbgdiv; 23 u32 tracediv; 24 u32 l4src; 25 26 /* peripheral group */ 27 u32 peri_vco_base; 28 u32 emac0clk; 29 u32 emac1clk; 30 u32 perqspiclk; 31 u32 pernandsdmmcclk; 32 u32 perbaseclk; 33 u32 s2fuser1clk; 34 u32 perdiv; 35 u32 gpiodiv; 36 u32 persrc; 37 38 /* sdram pll group */ 39 u32 sdram_vco_base; 40 u32 ddrdqsclk; 41 u32 ddr2xdqsclk; 42 u32 ddrdqclk; 43 u32 s2fuser2clk; 44 45 /* altera group */ 46 u32 altera_grp_mpuclk; 47 }; 48 49 struct socfpga_clock_manager_main_pll { 50 u32 vco; 51 u32 misc; 52 u32 mpuclk; 53 u32 mainclk; 54 u32 dbgatclk; 55 u32 mainqspiclk; 56 u32 mainnandsdmmcclk; 57 u32 cfgs2fuser0clk; 58 u32 en; 59 u32 maindiv; 60 u32 dbgdiv; 61 u32 tracediv; 62 u32 l4src; 63 u32 stat; 64 u32 _pad_0x38_0x40[2]; 65 }; 66 67 struct socfpga_clock_manager_per_pll { 68 u32 vco; 69 u32 misc; 70 u32 emac0clk; 71 u32 emac1clk; 72 u32 perqspiclk; 73 u32 pernandsdmmcclk; 74 u32 perbaseclk; 75 u32 s2fuser1clk; 76 u32 en; 77 u32 div; 78 u32 gpiodiv; 79 u32 src; 80 u32 stat; 81 u32 _pad_0x34_0x40[3]; 82 }; 83 84 struct socfpga_clock_manager_sdr_pll { 85 u32 vco; 86 u32 ctrl; 87 u32 ddrdqsclk; 88 u32 ddr2xdqsclk; 89 u32 ddrdqclk; 90 u32 s2fuser2clk; 91 u32 en; 92 u32 stat; 93 }; 94 95 struct socfpga_clock_manager_altera { 96 u32 mpuclk; 97 u32 mainclk; 98 }; 99 100 struct socfpga_clock_manager { 101 u32 ctrl; 102 u32 bypass; 103 u32 inter; 104 u32 intren; 105 u32 dbctrl; 106 u32 stat; 107 u32 _pad_0x18_0x3f[10]; 108 struct socfpga_clock_manager_main_pll main_pll; 109 struct socfpga_clock_manager_per_pll per_pll; 110 struct socfpga_clock_manager_sdr_pll sdr_pll; 111 struct socfpga_clock_manager_altera altera; 112 u32 _pad_0xe8_0x200[70]; 113 }; 114 115 /* Clock speed accessors */ 116 unsigned long cm_get_mpu_clk_hz(void); 117 unsigned long cm_get_sdram_clk_hz(void); 118 unsigned int cm_get_l4_sp_clk_hz(void); 119 unsigned int cm_get_mmc_controller_clk_hz(void); 120 unsigned int cm_get_qspi_controller_clk_hz(void); 121 unsigned int cm_get_spi_controller_clk_hz(void); 122 const unsigned int cm_get_osc_clk_hz(const int osc); 123 const unsigned int cm_get_f2s_per_ref_clk_hz(void); 124 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); 125 126 /* Clock configuration accessors */ 127 int cm_basic_init(const struct cm_config * const cfg); 128 const struct cm_config * const cm_get_default_config(void); 129 #endif /* __ASSEMBLER__ */ 130 131 #define LOCKED_MASK \ 132 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ 133 CLKMGR_INTER_PERPLLLOCKED_MASK | \ 134 CLKMGR_INTER_MAINPLLLOCKED_MASK) 135 136 #define CLKMGR_CTRL_SAFEMODE BIT(0) 137 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 138 139 #define CLKMGR_BYPASS_PERPLLSRC BIT(4) 140 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 141 #define CLKMGR_BYPASS_PERPLL BIT(3) 142 #define CLKMGR_BYPASS_PERPLL_OFFSET 3 143 #define CLKMGR_BYPASS_SDRPLLSRC BIT(2) 144 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 145 #define CLKMGR_BYPASS_SDRPLL BIT(1) 146 #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 147 #define CLKMGR_BYPASS_MAINPLL BIT(0) 148 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 149 150 #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3) 151 #define CLKMGR_INTER_PERPLLLOST_MASK BIT(4) 152 #define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5) 153 #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6) 154 #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7) 155 #define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8) 156 157 #define CLKMGR_STAT_BUSY BIT(0) 158 159 /* Main PLL */ 160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) 161 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 162 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 163 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 164 #define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) 165 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 166 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 167 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 168 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 169 #define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) 170 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 171 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 172 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 173 174 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 175 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 176 177 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 178 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 179 180 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 181 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 182 183 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 184 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 185 186 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 187 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 188 189 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 190 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 191 192 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) 193 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4) 194 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5) 195 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6) 196 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7) 197 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9) 198 199 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 200 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 201 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 202 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 203 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 204 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 205 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 206 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 207 208 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 209 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 210 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 211 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 212 213 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 214 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 215 216 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) 217 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 218 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) 219 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 220 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 221 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 222 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 223 224 /* Per PLL */ 225 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 226 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 227 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 228 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 229 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 230 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 231 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 232 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 233 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 234 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 235 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 236 237 #define CLKMGR_VCO_SSRC_EOSC1 0x0 238 #define CLKMGR_VCO_SSRC_EOSC2 0x1 239 #define CLKMGR_VCO_SSRC_F2S 0x2 240 241 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 242 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 243 244 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 245 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 246 247 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 248 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 249 250 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 251 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 252 253 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 254 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 255 256 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 257 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 258 259 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 260 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 261 262 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 263 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 264 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 265 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 266 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 267 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 268 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 269 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 270 271 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 272 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 273 274 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 275 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 276 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 277 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 278 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 279 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 280 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 281 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 282 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 283 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2 284 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0 285 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 286 #define CLKMGR_QSPI_CLK_SRC_PER 0x2 287 288 /* SDR PLL */ 289 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 290 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 291 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 292 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 293 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) 294 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 295 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 296 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 297 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31) 298 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 299 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 300 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 301 302 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 303 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 304 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 305 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 306 307 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 308 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 309 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 310 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 311 312 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 313 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 314 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 315 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 316 317 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 318 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 319 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 320 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 321 322 #endif /* _CLOCK_MANAGER_GEN5_H_ */ 323