1 /* 2 * Copyright (C) 2013 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CLOCK_MANAGER_H_ 8 #define _CLOCK_MANAGER_H_ 9 10 #ifndef __ASSEMBLER__ 11 /* Clock speed accessors */ 12 unsigned long cm_get_mpu_clk_hz(void); 13 unsigned long cm_get_sdram_clk_hz(void); 14 unsigned int cm_get_l4_sp_clk_hz(void); 15 unsigned int cm_get_mmc_controller_clk_hz(void); 16 unsigned int cm_get_qspi_controller_clk_hz(void); 17 unsigned int cm_get_spi_controller_clk_hz(void); 18 #endif 19 20 typedef struct { 21 /* main group */ 22 uint32_t main_vco_base; 23 uint32_t mpuclk; 24 uint32_t mainclk; 25 uint32_t dbgatclk; 26 uint32_t mainqspiclk; 27 uint32_t mainnandsdmmcclk; 28 uint32_t cfg2fuser0clk; 29 uint32_t maindiv; 30 uint32_t dbgdiv; 31 uint32_t tracediv; 32 uint32_t l4src; 33 34 /* peripheral group */ 35 uint32_t peri_vco_base; 36 uint32_t emac0clk; 37 uint32_t emac1clk; 38 uint32_t perqspiclk; 39 uint32_t pernandsdmmcclk; 40 uint32_t perbaseclk; 41 uint32_t s2fuser1clk; 42 uint32_t perdiv; 43 uint32_t gpiodiv; 44 uint32_t persrc; 45 46 /* sdram pll group */ 47 uint32_t sdram_vco_base; 48 uint32_t ddrdqsclk; 49 uint32_t ddr2xdqsclk; 50 uint32_t ddrdqclk; 51 uint32_t s2fuser2clk; 52 } cm_config_t; 53 54 extern void cm_basic_init(const cm_config_t *cfg); 55 56 struct socfpga_clock_manager_main_pll { 57 u32 vco; 58 u32 misc; 59 u32 mpuclk; 60 u32 mainclk; 61 u32 dbgatclk; 62 u32 mainqspiclk; 63 u32 mainnandsdmmcclk; 64 u32 cfgs2fuser0clk; 65 u32 en; 66 u32 maindiv; 67 u32 dbgdiv; 68 u32 tracediv; 69 u32 l4src; 70 u32 stat; 71 u32 _pad_0x38_0x40[2]; 72 }; 73 74 struct socfpga_clock_manager_per_pll { 75 u32 vco; 76 u32 misc; 77 u32 emac0clk; 78 u32 emac1clk; 79 u32 perqspiclk; 80 u32 pernandsdmmcclk; 81 u32 perbaseclk; 82 u32 s2fuser1clk; 83 u32 en; 84 u32 div; 85 u32 gpiodiv; 86 u32 src; 87 u32 stat; 88 u32 _pad_0x34_0x40[3]; 89 }; 90 91 struct socfpga_clock_manager_sdr_pll { 92 u32 vco; 93 u32 ctrl; 94 u32 ddrdqsclk; 95 u32 ddr2xdqsclk; 96 u32 ddrdqclk; 97 u32 s2fuser2clk; 98 u32 en; 99 u32 stat; 100 }; 101 102 struct socfpga_clock_manager_altera { 103 u32 mpuclk; 104 u32 mainclk; 105 }; 106 107 struct socfpga_clock_manager { 108 u32 ctrl; 109 u32 bypass; 110 u32 inter; 111 u32 intren; 112 u32 dbctrl; 113 u32 stat; 114 u32 _pad_0x18_0x3f[10]; 115 struct socfpga_clock_manager_main_pll main_pll; 116 struct socfpga_clock_manager_per_pll per_pll; 117 struct socfpga_clock_manager_sdr_pll sdr_pll; 118 struct socfpga_clock_manager_altera altera; 119 u32 _pad_0xe8_0x200[70]; 120 }; 121 122 #define CLKMGR_CTRL_SAFEMODE (1 << 0) 123 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 124 125 #define CLKMGR_BYPASS_PERPLLSRC (1 << 4) 126 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 127 #define CLKMGR_BYPASS_PERPLL (1 << 3) 128 #define CLKMGR_BYPASS_PERPLL_OFFSET 3 129 #define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) 130 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 131 #define CLKMGR_BYPASS_SDRPLL (1 << 1) 132 #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 133 #define CLKMGR_BYPASS_MAINPLL (1 << 0) 134 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 135 136 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 137 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 138 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 139 #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 140 #define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 141 #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 142 143 #define CLKMGR_STAT_BUSY (1 << 0) 144 145 /* Main PLL */ 146 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) 147 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 148 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 149 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 150 #define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) 151 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 152 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 153 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 154 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 155 #define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) 156 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 157 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 158 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 159 160 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 161 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 162 163 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 164 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 165 166 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 167 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 168 169 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 170 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 171 172 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 173 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 174 175 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 176 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 177 178 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 179 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 180 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 181 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 182 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 183 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 184 185 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 186 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 187 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 188 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 189 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 190 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 191 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 192 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 193 194 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 195 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 196 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 197 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 198 199 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 200 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 201 202 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) 203 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 204 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) 205 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 206 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 207 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 208 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 209 210 /* Per PLL */ 211 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 212 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 213 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 214 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 215 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 216 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 217 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 218 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 219 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 220 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 221 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 222 223 #define CLKMGR_VCO_SSRC_EOSC1 0x0 224 #define CLKMGR_VCO_SSRC_EOSC2 0x1 225 #define CLKMGR_VCO_SSRC_F2S 0x2 226 227 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 228 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 229 230 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 231 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 232 233 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 234 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 235 236 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 237 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 238 239 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 240 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 241 242 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 243 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 244 245 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 246 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 247 248 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 249 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 250 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 251 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 252 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 253 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 254 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 255 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 256 257 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 258 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 259 260 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 261 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 262 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 263 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 264 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 265 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 266 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 267 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 268 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 269 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2 270 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0 271 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 272 #define CLKMGR_QSPI_CLK_SRC_PER 0x2 273 274 /* SDR PLL */ 275 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 276 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 277 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 278 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 279 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) 280 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 281 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 282 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 283 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 284 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 285 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 286 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 287 288 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 289 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 290 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 291 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 292 293 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 294 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 295 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 296 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 297 298 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 299 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 300 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 301 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 302 303 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 304 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 305 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 306 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 307 308 #endif /* _CLOCK_MANAGER_H_ */ 309