1*30088b09SMasahiro Yamada /* 2*30088b09SMasahiro Yamada * Copyright (C) 2013 Altera Corporation <www.altera.com> 3*30088b09SMasahiro Yamada * 4*30088b09SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*30088b09SMasahiro Yamada */ 6*30088b09SMasahiro Yamada 7*30088b09SMasahiro Yamada #ifndef _CLOCK_MANAGER_H_ 8*30088b09SMasahiro Yamada #define _CLOCK_MANAGER_H_ 9*30088b09SMasahiro Yamada 10*30088b09SMasahiro Yamada #ifndef __ASSEMBLER__ 11*30088b09SMasahiro Yamada /* Clock speed accessors */ 12*30088b09SMasahiro Yamada unsigned long cm_get_mpu_clk_hz(void); 13*30088b09SMasahiro Yamada unsigned long cm_get_sdram_clk_hz(void); 14*30088b09SMasahiro Yamada unsigned int cm_get_l4_sp_clk_hz(void); 15*30088b09SMasahiro Yamada unsigned int cm_get_mmc_controller_clk_hz(void); 16*30088b09SMasahiro Yamada unsigned int cm_get_qspi_controller_clk_hz(void); 17*30088b09SMasahiro Yamada unsigned int cm_get_spi_controller_clk_hz(void); 18*30088b09SMasahiro Yamada #endif 19*30088b09SMasahiro Yamada 20*30088b09SMasahiro Yamada typedef struct { 21*30088b09SMasahiro Yamada /* main group */ 22*30088b09SMasahiro Yamada uint32_t main_vco_base; 23*30088b09SMasahiro Yamada uint32_t mpuclk; 24*30088b09SMasahiro Yamada uint32_t mainclk; 25*30088b09SMasahiro Yamada uint32_t dbgatclk; 26*30088b09SMasahiro Yamada uint32_t mainqspiclk; 27*30088b09SMasahiro Yamada uint32_t mainnandsdmmcclk; 28*30088b09SMasahiro Yamada uint32_t cfg2fuser0clk; 29*30088b09SMasahiro Yamada uint32_t maindiv; 30*30088b09SMasahiro Yamada uint32_t dbgdiv; 31*30088b09SMasahiro Yamada uint32_t tracediv; 32*30088b09SMasahiro Yamada uint32_t l4src; 33*30088b09SMasahiro Yamada 34*30088b09SMasahiro Yamada /* peripheral group */ 35*30088b09SMasahiro Yamada uint32_t peri_vco_base; 36*30088b09SMasahiro Yamada uint32_t emac0clk; 37*30088b09SMasahiro Yamada uint32_t emac1clk; 38*30088b09SMasahiro Yamada uint32_t perqspiclk; 39*30088b09SMasahiro Yamada uint32_t pernandsdmmcclk; 40*30088b09SMasahiro Yamada uint32_t perbaseclk; 41*30088b09SMasahiro Yamada uint32_t s2fuser1clk; 42*30088b09SMasahiro Yamada uint32_t perdiv; 43*30088b09SMasahiro Yamada uint32_t gpiodiv; 44*30088b09SMasahiro Yamada uint32_t persrc; 45*30088b09SMasahiro Yamada 46*30088b09SMasahiro Yamada /* sdram pll group */ 47*30088b09SMasahiro Yamada uint32_t sdram_vco_base; 48*30088b09SMasahiro Yamada uint32_t ddrdqsclk; 49*30088b09SMasahiro Yamada uint32_t ddr2xdqsclk; 50*30088b09SMasahiro Yamada uint32_t ddrdqclk; 51*30088b09SMasahiro Yamada uint32_t s2fuser2clk; 52*30088b09SMasahiro Yamada } cm_config_t; 53*30088b09SMasahiro Yamada 54*30088b09SMasahiro Yamada extern void cm_basic_init(const cm_config_t *cfg); 55*30088b09SMasahiro Yamada 56*30088b09SMasahiro Yamada struct socfpga_clock_manager_main_pll { 57*30088b09SMasahiro Yamada u32 vco; 58*30088b09SMasahiro Yamada u32 misc; 59*30088b09SMasahiro Yamada u32 mpuclk; 60*30088b09SMasahiro Yamada u32 mainclk; 61*30088b09SMasahiro Yamada u32 dbgatclk; 62*30088b09SMasahiro Yamada u32 mainqspiclk; 63*30088b09SMasahiro Yamada u32 mainnandsdmmcclk; 64*30088b09SMasahiro Yamada u32 cfgs2fuser0clk; 65*30088b09SMasahiro Yamada u32 en; 66*30088b09SMasahiro Yamada u32 maindiv; 67*30088b09SMasahiro Yamada u32 dbgdiv; 68*30088b09SMasahiro Yamada u32 tracediv; 69*30088b09SMasahiro Yamada u32 l4src; 70*30088b09SMasahiro Yamada u32 stat; 71*30088b09SMasahiro Yamada u32 _pad_0x38_0x40[2]; 72*30088b09SMasahiro Yamada }; 73*30088b09SMasahiro Yamada 74*30088b09SMasahiro Yamada struct socfpga_clock_manager_per_pll { 75*30088b09SMasahiro Yamada u32 vco; 76*30088b09SMasahiro Yamada u32 misc; 77*30088b09SMasahiro Yamada u32 emac0clk; 78*30088b09SMasahiro Yamada u32 emac1clk; 79*30088b09SMasahiro Yamada u32 perqspiclk; 80*30088b09SMasahiro Yamada u32 pernandsdmmcclk; 81*30088b09SMasahiro Yamada u32 perbaseclk; 82*30088b09SMasahiro Yamada u32 s2fuser1clk; 83*30088b09SMasahiro Yamada u32 en; 84*30088b09SMasahiro Yamada u32 div; 85*30088b09SMasahiro Yamada u32 gpiodiv; 86*30088b09SMasahiro Yamada u32 src; 87*30088b09SMasahiro Yamada u32 stat; 88*30088b09SMasahiro Yamada u32 _pad_0x34_0x40[3]; 89*30088b09SMasahiro Yamada }; 90*30088b09SMasahiro Yamada 91*30088b09SMasahiro Yamada struct socfpga_clock_manager_sdr_pll { 92*30088b09SMasahiro Yamada u32 vco; 93*30088b09SMasahiro Yamada u32 ctrl; 94*30088b09SMasahiro Yamada u32 ddrdqsclk; 95*30088b09SMasahiro Yamada u32 ddr2xdqsclk; 96*30088b09SMasahiro Yamada u32 ddrdqclk; 97*30088b09SMasahiro Yamada u32 s2fuser2clk; 98*30088b09SMasahiro Yamada u32 en; 99*30088b09SMasahiro Yamada u32 stat; 100*30088b09SMasahiro Yamada }; 101*30088b09SMasahiro Yamada 102*30088b09SMasahiro Yamada struct socfpga_clock_manager_altera { 103*30088b09SMasahiro Yamada u32 mpuclk; 104*30088b09SMasahiro Yamada u32 mainclk; 105*30088b09SMasahiro Yamada }; 106*30088b09SMasahiro Yamada 107*30088b09SMasahiro Yamada struct socfpga_clock_manager { 108*30088b09SMasahiro Yamada u32 ctrl; 109*30088b09SMasahiro Yamada u32 bypass; 110*30088b09SMasahiro Yamada u32 inter; 111*30088b09SMasahiro Yamada u32 intren; 112*30088b09SMasahiro Yamada u32 dbctrl; 113*30088b09SMasahiro Yamada u32 stat; 114*30088b09SMasahiro Yamada u32 _pad_0x18_0x3f[10]; 115*30088b09SMasahiro Yamada struct socfpga_clock_manager_main_pll main_pll; 116*30088b09SMasahiro Yamada struct socfpga_clock_manager_per_pll per_pll; 117*30088b09SMasahiro Yamada struct socfpga_clock_manager_sdr_pll sdr_pll; 118*30088b09SMasahiro Yamada struct socfpga_clock_manager_altera altera; 119*30088b09SMasahiro Yamada u32 _pad_0xe8_0x200[70]; 120*30088b09SMasahiro Yamada }; 121*30088b09SMasahiro Yamada 122*30088b09SMasahiro Yamada #define CLKMGR_CTRL_SAFEMODE (1 << 0) 123*30088b09SMasahiro Yamada #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 124*30088b09SMasahiro Yamada 125*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_PERPLLSRC (1 << 4) 126*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 127*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_PERPLL (1 << 3) 128*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_PERPLL_OFFSET 3 129*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) 130*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 131*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_SDRPLL (1 << 1) 132*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 133*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_MAINPLL (1 << 0) 134*30088b09SMasahiro Yamada #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 135*30088b09SMasahiro Yamada 136*30088b09SMasahiro Yamada #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 137*30088b09SMasahiro Yamada #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 138*30088b09SMasahiro Yamada #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 139*30088b09SMasahiro Yamada #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 140*30088b09SMasahiro Yamada #define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 141*30088b09SMasahiro Yamada #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 142*30088b09SMasahiro Yamada 143*30088b09SMasahiro Yamada #define CLKMGR_STAT_BUSY (1 << 0) 144*30088b09SMasahiro Yamada 145*30088b09SMasahiro Yamada /* Main PLL */ 146*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) 147*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 148*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 149*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 150*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) 151*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 152*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 153*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 154*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 155*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) 156*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 157*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 158*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 159*30088b09SMasahiro Yamada 160*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 161*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 162*30088b09SMasahiro Yamada 163*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 164*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 165*30088b09SMasahiro Yamada 166*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 167*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 168*30088b09SMasahiro Yamada 169*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 170*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 171*30088b09SMasahiro Yamada 172*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 173*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 174*30088b09SMasahiro Yamada 175*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 176*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 177*30088b09SMasahiro Yamada 178*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 179*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 180*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 181*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 182*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 183*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 184*30088b09SMasahiro Yamada 185*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 186*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 187*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 188*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 189*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 190*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 191*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 192*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 193*30088b09SMasahiro Yamada 194*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 195*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 196*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 197*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 198*30088b09SMasahiro Yamada 199*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 200*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 201*30088b09SMasahiro Yamada 202*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) 203*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 204*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) 205*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 206*30088b09SMasahiro Yamada #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 207*30088b09SMasahiro Yamada #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 208*30088b09SMasahiro Yamada #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 209*30088b09SMasahiro Yamada 210*30088b09SMasahiro Yamada /* Per PLL */ 211*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 212*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 213*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 214*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 215*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 216*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 217*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 218*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 219*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 220*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 221*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 222*30088b09SMasahiro Yamada 223*30088b09SMasahiro Yamada #define CLKMGR_VCO_SSRC_EOSC1 0x0 224*30088b09SMasahiro Yamada #define CLKMGR_VCO_SSRC_EOSC2 0x1 225*30088b09SMasahiro Yamada #define CLKMGR_VCO_SSRC_F2S 0x2 226*30088b09SMasahiro Yamada 227*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 228*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 229*30088b09SMasahiro Yamada 230*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 231*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 232*30088b09SMasahiro Yamada 233*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 234*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 235*30088b09SMasahiro Yamada 236*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 237*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 238*30088b09SMasahiro Yamada 239*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 240*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 241*30088b09SMasahiro Yamada 242*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 243*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 244*30088b09SMasahiro Yamada 245*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 246*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 247*30088b09SMasahiro Yamada 248*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 249*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 250*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 251*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 252*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 253*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 254*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 255*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 256*30088b09SMasahiro Yamada 257*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 258*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 259*30088b09SMasahiro Yamada 260*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 261*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 262*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 263*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 264*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 265*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 266*30088b09SMasahiro Yamada #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 267*30088b09SMasahiro Yamada #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 268*30088b09SMasahiro Yamada #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 269*30088b09SMasahiro Yamada #define CLKMGR_SDMMC_CLK_SRC_PER 0x2 270*30088b09SMasahiro Yamada #define CLKMGR_QSPI_CLK_SRC_F2S 0x0 271*30088b09SMasahiro Yamada #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 272*30088b09SMasahiro Yamada #define CLKMGR_QSPI_CLK_SRC_PER 0x2 273*30088b09SMasahiro Yamada 274*30088b09SMasahiro Yamada /* SDR PLL */ 275*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 276*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 277*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 278*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 279*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) 280*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 281*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 282*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 283*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 284*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 285*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 286*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 287*30088b09SMasahiro Yamada 288*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 289*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 290*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 291*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 292*30088b09SMasahiro Yamada 293*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 294*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 295*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 296*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 297*30088b09SMasahiro Yamada 298*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 299*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 300*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 301*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 302*30088b09SMasahiro Yamada 303*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 304*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 305*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 306*30088b09SMasahiro Yamada #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 307*30088b09SMasahiro Yamada 308*30088b09SMasahiro Yamada #endif /* _CLOCK_MANAGER_H_ */ 309