1*beee6a30SMarek Vasut /* 2*beee6a30SMarek Vasut * Specialty padding for the Altera SoCFPGA preloader image 3*beee6a30SMarek Vasut * 4*beee6a30SMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 5*beee6a30SMarek Vasut */ 6*beee6a30SMarek Vasut 7*beee6a30SMarek Vasut #ifndef __BOOT0_H 8*beee6a30SMarek Vasut #define __BOOT0_H 9*beee6a30SMarek Vasut 10*beee6a30SMarek Vasut #ifdef CONFIG_SPL_BUILD 11*beee6a30SMarek Vasut #define ARM_SOC_BOOT0_HOOK \ 12*beee6a30SMarek Vasut .balignl 64,0xf33db33f; \ 13*beee6a30SMarek Vasut \ 14*beee6a30SMarek Vasut .word 0x1337c0d3; /* SoCFPGA preloader validation word */ \ 15*beee6a30SMarek Vasut .word 0xc01df00d; /* Version, flags, length */ \ 16*beee6a30SMarek Vasut .word 0xcafec0d3; /* Checksum, zero-pad */ \ 17*beee6a30SMarek Vasut nop; \ 18*beee6a30SMarek Vasut \ 19*beee6a30SMarek Vasut b reset; /* SoCFPGA jumps here */ \ 20*beee6a30SMarek Vasut nop; \ 21*beee6a30SMarek Vasut nop; \ 22*beee6a30SMarek Vasut nop; 23*beee6a30SMarek Vasut #else 24*beee6a30SMarek Vasut #define ARM_SOC_BOOT0_HOOK 25*beee6a30SMarek Vasut #endif 26*beee6a30SMarek Vasut 27*beee6a30SMarek Vasut 28*beee6a30SMarek Vasut #endif /* __BOOT0_H */ 29