1beee6a30SMarek Vasut /*
2beee6a30SMarek Vasut  * Specialty padding for the Altera SoCFPGA preloader image
3beee6a30SMarek Vasut  *
4beee6a30SMarek Vasut  * SPDX-License-Identifier:	GPL-2.0+
5beee6a30SMarek Vasut  */
6beee6a30SMarek Vasut 
7beee6a30SMarek Vasut #ifndef __BOOT0_H
8beee6a30SMarek Vasut #define __BOOT0_H
9beee6a30SMarek Vasut 
10*a002077dSPhilipp Tomsich _start:
11*a002077dSPhilipp Tomsich 	ARM_VECTORS
12*a002077dSPhilipp Tomsich 
13beee6a30SMarek Vasut #ifdef CONFIG_SPL_BUILD
144c0f3e7fSChee, Tien Fong 	.balignl 64,0xf33db33f;
15beee6a30SMarek Vasut 
164c0f3e7fSChee, Tien Fong 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
174c0f3e7fSChee, Tien Fong 	.word	0xc01df00d;	/* Version, flags, length */
184c0f3e7fSChee, Tien Fong 	.word	0xcafec0d3;	/* Checksum, zero-pad */
194c0f3e7fSChee, Tien Fong 	nop;
204c0f3e7fSChee, Tien Fong 
214c0f3e7fSChee, Tien Fong 	b reset;		/* SoCFPGA jumps here */
224c0f3e7fSChee, Tien Fong 	nop;
234c0f3e7fSChee, Tien Fong 	nop;
244c0f3e7fSChee, Tien Fong 	nop;
254c0f3e7fSChee, Tien Fong #endif
26beee6a30SMarek Vasut 
27beee6a30SMarek Vasut #endif /* __BOOT0_H */
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