1beee6a30SMarek Vasut /*
2beee6a30SMarek Vasut  * Specialty padding for the Altera SoCFPGA preloader image
3beee6a30SMarek Vasut  *
4beee6a30SMarek Vasut  * SPDX-License-Identifier:	GPL-2.0+
5beee6a30SMarek Vasut  */
6beee6a30SMarek Vasut 
7beee6a30SMarek Vasut #ifndef __BOOT0_H
8beee6a30SMarek Vasut #define __BOOT0_H
9beee6a30SMarek Vasut 
10beee6a30SMarek Vasut #ifdef CONFIG_SPL_BUILD
11*4c0f3e7fSChee, Tien Fong 	.balignl 64,0xf33db33f;
12beee6a30SMarek Vasut 
13*4c0f3e7fSChee, Tien Fong 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
14*4c0f3e7fSChee, Tien Fong 	.word	0xc01df00d;	/* Version, flags, length */
15*4c0f3e7fSChee, Tien Fong 	.word	0xcafec0d3;	/* Checksum, zero-pad */
16*4c0f3e7fSChee, Tien Fong 	nop;
17*4c0f3e7fSChee, Tien Fong 
18*4c0f3e7fSChee, Tien Fong 	b reset;		/* SoCFPGA jumps here */
19*4c0f3e7fSChee, Tien Fong 	nop;
20*4c0f3e7fSChee, Tien Fong 	nop;
21*4c0f3e7fSChee, Tien Fong 	nop;
22*4c0f3e7fSChee, Tien Fong #endif
23beee6a30SMarek Vasut 
24beee6a30SMarek Vasut #endif /* __BOOT0_H */
25