1 /* 2 * Copyright (C) 2014 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ 8 #define _SOCFPGA_A10_BASE_HARDWARE_H_ 9 10 #define SOCFPGA_EMAC0_ADDRESS 0xff800000 11 #define SOCFPGA_EMAC1_ADDRESS 0xff802000 12 #define SOCFPGA_EMAC2_ADDRESS 0xff804000 13 #define SOCFPGA_SDMMC_ADDRESS 0xff808000 14 #define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 15 #define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 16 #define SOCFPGA_UART1_ADDRESS 0xffc02100 17 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 18 #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 19 #define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 20 #define SOCFPGA_L4WD0_ADDRESS 0xffd00200 21 #define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 22 #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 23 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 24 #define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300 25 #define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400 26 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 27 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 28 #define SOCFPGA_MPUSCU_ADDRESS 0xffffc000 29 #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 30 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 31 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 32 33 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 34 #define SOCFPGA_UART0_ADDRESS 0xffc02000 35 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 36 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 37 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 38 39 #define SOCFPGA_SDR_ADDRESS 0xffcfb000 40 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 41 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 42 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 43 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 44 45 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ 46