1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * All rights reserved. 4 * 5 * This file contains only support functions used also by the SoCFPGA 6 * platform code, the real meat is located in drivers/fpga/socfpga.c . 7 * 8 * SPDX-License-Identifier: BSD-3-Clause 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <linux/errno.h> 14 #include <asm/arch/fpga_manager.h> 15 #include <asm/arch/reset_manager.h> 16 #include <asm/arch/system_manager.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* Timeout count */ 21 #define FPGA_TIMEOUT_CNT 0x1000000 22 23 static struct socfpga_fpga_manager *fpgamgr_regs = 24 (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; 25 26 /* Check whether FPGA Init_Done signal is high */ 27 static int is_fpgamgr_initdone_high(void) 28 { 29 unsigned long val; 30 31 val = readl(&fpgamgr_regs->gpio_ext_porta); 32 return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; 33 } 34 35 /* Get the FPGA mode */ 36 int fpgamgr_get_mode(void) 37 { 38 unsigned long val; 39 40 val = readl(&fpgamgr_regs->stat); 41 return val & FPGAMGRREGS_STAT_MODE_MASK; 42 } 43 44 /* Check whether FPGA is ready to be accessed */ 45 int fpgamgr_test_fpga_ready(void) 46 { 47 /* Check for init done signal */ 48 if (!is_fpgamgr_initdone_high()) 49 return 0; 50 51 /* Check again to avoid false glitches */ 52 if (!is_fpgamgr_initdone_high()) 53 return 0; 54 55 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) 56 return 0; 57 58 return 1; 59 } 60 61 /* Poll until FPGA is ready to be accessed or timeout occurred */ 62 int fpgamgr_poll_fpga_ready(void) 63 { 64 unsigned long i; 65 66 /* If FPGA is blank, wait till WD invoke warm reset */ 67 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { 68 /* check for init done signal */ 69 if (!is_fpgamgr_initdone_high()) 70 continue; 71 /* check again to avoid false glitches */ 72 if (!is_fpgamgr_initdone_high()) 73 continue; 74 return 1; 75 } 76 77 return 0; 78 } 79