1 /*
2  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <dm.h>
10 #include <asm/arch/clock_manager.h>
11 #include <wait_bit.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 static const struct socfpga_clock_manager *clock_manager_base =
16 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
17 
18 /*
19  * function to write the bypass register which requires a poll of the
20  * busy bit
21  */
22 static void cm_write_bypass(u32 val)
23 {
24 	writel(val, &clock_manager_base->bypass);
25 	cm_wait_for_fsm();
26 }
27 
28 /* function to write the ctrl register which requires a poll of the busy bit */
29 static void cm_write_ctrl(u32 val)
30 {
31 	writel(val, &clock_manager_base->ctrl);
32 	cm_wait_for_fsm();
33 }
34 
35 /* function to write a clock register that has phase information */
36 static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
37 {
38 	int ret;
39 
40 	/* poll until phase is zero */
41 	ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
42 	if (ret)
43 		return ret;
44 
45 	writel(value, reg_address);
46 
47 	return wait_for_bit_le32(reg_address, mask, false, 20000, false);
48 }
49 
50 /*
51  * Setup clocks while making no assumptions about previous state of the clocks.
52  *
53  * Start by being paranoid and gate all sw managed clocks
54  * Put all plls in bypass
55  * Put all plls VCO registers back to reset value (bandgap power down).
56  * Put peripheral and main pll src to reset value to avoid glitch.
57  * Delay 5 us.
58  * Deassert bandgap power down and set numerator and denominator
59  * Start 7 us timer.
60  * set internal dividers
61  * Wait for 7 us timer.
62  * Enable plls
63  * Set external dividers while plls are locking
64  * Wait for pll lock
65  * Assert/deassert outreset all.
66  * Take all pll's out of bypass
67  * Clear safe mode
68  * set source main and peripheral clocks
69  * Ungate clocks
70  */
71 
72 int cm_basic_init(const struct cm_config * const cfg)
73 {
74 	unsigned long end;
75 	int ret;
76 
77 	/* Start by being paranoid and gate all sw managed clocks */
78 
79 	/*
80 	 * We need to disable nandclk
81 	 * and then do another apb access before disabling
82 	 * gatting off the rest of the periperal clocks.
83 	 */
84 	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
85 		readl(&clock_manager_base->per_pll.en),
86 		&clock_manager_base->per_pll.en);
87 
88 	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
89 	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
90 		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
91 		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
92 		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
93 		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
94 		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
95 		&clock_manager_base->main_pll.en);
96 
97 	writel(0, &clock_manager_base->sdr_pll.en);
98 
99 	/* now we can gate off the rest of the peripheral clocks */
100 	writel(0, &clock_manager_base->per_pll.en);
101 
102 	/* Put all plls in bypass */
103 	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
104 			CLKMGR_BYPASS_MAINPLL);
105 
106 	/* Put all plls VCO registers back to reset value. */
107 	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
108 	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
109 	       &clock_manager_base->main_pll.vco);
110 	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
111 	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
112 	       &clock_manager_base->per_pll.vco);
113 	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
114 	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
115 	       &clock_manager_base->sdr_pll.vco);
116 
117 	/*
118 	 * The clocks to the flash devices and the L4_MAIN clocks can
119 	 * glitch when coming out of safe mode if their source values
120 	 * are different from their reset value.  So the trick it to
121 	 * put them back to their reset state, and change input
122 	 * after exiting safe mode but before ungating the clocks.
123 	 */
124 	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
125 	       &clock_manager_base->per_pll.src);
126 	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
127 	       &clock_manager_base->main_pll.l4src);
128 
129 	/* read back for the required 5 us delay. */
130 	readl(&clock_manager_base->main_pll.vco);
131 	readl(&clock_manager_base->per_pll.vco);
132 	readl(&clock_manager_base->sdr_pll.vco);
133 
134 
135 	/*
136 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
137 	 * with numerator and denominator.
138 	 */
139 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
140 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
141 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
142 
143 	/*
144 	 * Time starts here. Must wait 7 us from
145 	 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
146 	 */
147 	end = timer_get_us() + 7;
148 
149 	/* main mpu */
150 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
151 
152 	/* altera group mpuclk */
153 	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
154 
155 	/* main main clock */
156 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
157 
158 	/* main for dbg */
159 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
160 
161 	/* main for cfgs2fuser0clk */
162 	writel(cfg->cfg2fuser0clk,
163 	       &clock_manager_base->main_pll.cfgs2fuser0clk);
164 
165 	/* Peri emac0 50 MHz default to RMII */
166 	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
167 
168 	/* Peri emac1 50 MHz default to RMII */
169 	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
170 
171 	/* Peri QSPI */
172 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
173 
174 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
175 
176 	/* Peri pernandsdmmcclk */
177 	writel(cfg->mainnandsdmmcclk,
178 	       &clock_manager_base->main_pll.mainnandsdmmcclk);
179 
180 	writel(cfg->pernandsdmmcclk,
181 	       &clock_manager_base->per_pll.pernandsdmmcclk);
182 
183 	/* Peri perbaseclk */
184 	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
185 
186 	/* Peri s2fuser1clk */
187 	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
188 
189 	/* 7 us must have elapsed before we can enable the VCO */
190 	while (timer_get_us() < end)
191 		;
192 
193 	/* Enable vco */
194 	/* main pll vco */
195 	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
196 	       &clock_manager_base->main_pll.vco);
197 
198 	/* periferal pll */
199 	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
200 	       &clock_manager_base->per_pll.vco);
201 
202 	/* sdram pll vco */
203 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
204 	       &clock_manager_base->sdr_pll.vco);
205 
206 	/* L3 MP and L3 SP */
207 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
208 
209 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
210 
211 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
212 
213 	/* L4 MP, L4 SP, can0, and can1 */
214 	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
215 
216 	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
217 
218 	cm_wait_for_lock(LOCKED_MASK);
219 
220 	/* write the sdram clock counters before toggling outreset all */
221 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
222 	       &clock_manager_base->sdr_pll.ddrdqsclk);
223 
224 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
225 	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
226 
227 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
228 	       &clock_manager_base->sdr_pll.ddrdqclk);
229 
230 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
231 	       &clock_manager_base->sdr_pll.s2fuser2clk);
232 
233 	/*
234 	 * after locking, but before taking out of bypass
235 	 * assert/deassert outresetall
236 	 */
237 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);
238 
239 	/* assert main outresetall */
240 	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
241 	       &clock_manager_base->main_pll.vco);
242 
243 	u32 periphvco = readl(&clock_manager_base->per_pll.vco);
244 
245 	/* assert pheriph outresetall */
246 	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
247 	       &clock_manager_base->per_pll.vco);
248 
249 	/* assert sdram outresetall */
250 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
251 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
252 		&clock_manager_base->sdr_pll.vco);
253 
254 	/* deassert main outresetall */
255 	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
256 	       &clock_manager_base->main_pll.vco);
257 
258 	/* deassert pheriph outresetall */
259 	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
260 	       &clock_manager_base->per_pll.vco);
261 
262 	/* deassert sdram outresetall */
263 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
264 	       &clock_manager_base->sdr_pll.vco);
265 
266 	/*
267 	 * now that we've toggled outreset all, all the clocks
268 	 * are aligned nicely; so we can change any phase.
269 	 */
270 	ret = cm_write_with_phase(cfg->ddrdqsclk,
271 				  &clock_manager_base->sdr_pll.ddrdqsclk,
272 				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
273 	if (ret)
274 		return ret;
275 
276 	/* SDRAM DDR2XDQSCLK */
277 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
278 				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
279 				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
280 	if (ret)
281 		return ret;
282 
283 	ret = cm_write_with_phase(cfg->ddrdqclk,
284 				  &clock_manager_base->sdr_pll.ddrdqclk,
285 				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
286 	if (ret)
287 		return ret;
288 
289 	ret = cm_write_with_phase(cfg->s2fuser2clk,
290 				  &clock_manager_base->sdr_pll.s2fuser2clk,
291 				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
292 	if (ret)
293 		return ret;
294 
295 	/* Take all three PLLs out of bypass when safe mode is cleared. */
296 	cm_write_bypass(0);
297 
298 	/* clear safe mode */
299 	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
300 
301 	/*
302 	 * now that safe mode is clear with clocks gated
303 	 * it safe to change the source mux for the flashes the the L4_MAIN
304 	 */
305 	writel(cfg->persrc, &clock_manager_base->per_pll.src);
306 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
307 
308 	/* Now ungate non-hw-managed clocks */
309 	writel(~0, &clock_manager_base->main_pll.en);
310 	writel(~0, &clock_manager_base->per_pll.en);
311 	writel(~0, &clock_manager_base->sdr_pll.en);
312 
313 	/* Clear the loss of lock bits (write 1 to clear) */
314 	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
315 	       CLKMGR_INTER_MAINPLLLOST_MASK,
316 	       &clock_manager_base->inter);
317 
318 	return 0;
319 }
320 
321 static unsigned int cm_get_main_vco_clk_hz(void)
322 {
323 	u32 reg, clock;
324 
325 	/* get the main VCO clock */
326 	reg = readl(&clock_manager_base->main_pll.vco);
327 	clock = cm_get_osc_clk_hz(1);
328 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
329 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
330 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
331 		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
332 
333 	return clock;
334 }
335 
336 static unsigned int cm_get_per_vco_clk_hz(void)
337 {
338 	u32 reg, clock = 0;
339 
340 	/* identify PER PLL clock source */
341 	reg = readl(&clock_manager_base->per_pll.vco);
342 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
343 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
344 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
345 		clock = cm_get_osc_clk_hz(1);
346 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
347 		clock = cm_get_osc_clk_hz(2);
348 	else if (reg == CLKMGR_VCO_SSRC_F2S)
349 		clock = cm_get_f2s_per_ref_clk_hz();
350 
351 	/* get the PER VCO clock */
352 	reg = readl(&clock_manager_base->per_pll.vco);
353 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
354 		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
355 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
356 		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
357 
358 	return clock;
359 }
360 
361 unsigned long cm_get_mpu_clk_hz(void)
362 {
363 	u32 reg, clock;
364 
365 	clock = cm_get_main_vco_clk_hz();
366 
367 	/* get the MPU clock */
368 	reg = readl(&clock_manager_base->altera.mpuclk);
369 	clock /= (reg + 1);
370 	reg = readl(&clock_manager_base->main_pll.mpuclk);
371 	clock /= (reg + 1);
372 	return clock;
373 }
374 
375 unsigned long cm_get_sdram_clk_hz(void)
376 {
377 	u32 reg, clock = 0;
378 
379 	/* identify SDRAM PLL clock source */
380 	reg = readl(&clock_manager_base->sdr_pll.vco);
381 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
382 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
383 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
384 		clock = cm_get_osc_clk_hz(1);
385 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
386 		clock = cm_get_osc_clk_hz(2);
387 	else if (reg == CLKMGR_VCO_SSRC_F2S)
388 		clock = cm_get_f2s_sdr_ref_clk_hz();
389 
390 	/* get the SDRAM VCO clock */
391 	reg = readl(&clock_manager_base->sdr_pll.vco);
392 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
393 		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
394 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
395 		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
396 
397 	/* get the SDRAM (DDR_DQS) clock */
398 	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
399 	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
400 	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
401 	clock /= (reg + 1);
402 
403 	return clock;
404 }
405 
406 unsigned int cm_get_l4_sp_clk_hz(void)
407 {
408 	u32 reg, clock = 0;
409 
410 	/* identify the source of L4 SP clock */
411 	reg = readl(&clock_manager_base->main_pll.l4src);
412 	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
413 	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
414 
415 	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
416 		clock = cm_get_main_vco_clk_hz();
417 
418 		/* get the clock prior L4 SP divider (main clk) */
419 		reg = readl(&clock_manager_base->altera.mainclk);
420 		clock /= (reg + 1);
421 		reg = readl(&clock_manager_base->main_pll.mainclk);
422 		clock /= (reg + 1);
423 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
424 		clock = cm_get_per_vco_clk_hz();
425 
426 		/* get the clock prior L4 SP divider (periph_base_clk) */
427 		reg = readl(&clock_manager_base->per_pll.perbaseclk);
428 		clock /= (reg + 1);
429 	}
430 
431 	/* get the L4 SP clock which supplied to UART */
432 	reg = readl(&clock_manager_base->main_pll.maindiv);
433 	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
434 	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
435 	clock = clock / (1 << reg);
436 
437 	return clock;
438 }
439 
440 unsigned int cm_get_mmc_controller_clk_hz(void)
441 {
442 	u32 reg, clock = 0;
443 
444 	/* identify the source of MMC clock */
445 	reg = readl(&clock_manager_base->per_pll.src);
446 	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
447 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
448 
449 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
450 		clock = cm_get_f2s_per_ref_clk_hz();
451 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
452 		clock = cm_get_main_vco_clk_hz();
453 
454 		/* get the SDMMC clock */
455 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
456 		clock /= (reg + 1);
457 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
458 		clock = cm_get_per_vco_clk_hz();
459 
460 		/* get the SDMMC clock */
461 		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
462 		clock /= (reg + 1);
463 	}
464 
465 	/* further divide by 4 as we have fixed divider at wrapper */
466 	clock /= 4;
467 	return clock;
468 }
469 
470 unsigned int cm_get_qspi_controller_clk_hz(void)
471 {
472 	u32 reg, clock = 0;
473 
474 	/* identify the source of QSPI clock */
475 	reg = readl(&clock_manager_base->per_pll.src);
476 	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
477 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
478 
479 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
480 		clock = cm_get_f2s_per_ref_clk_hz();
481 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
482 		clock = cm_get_main_vco_clk_hz();
483 
484 		/* get the qspi clock */
485 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
486 		clock /= (reg + 1);
487 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
488 		clock = cm_get_per_vco_clk_hz();
489 
490 		/* get the qspi clock */
491 		reg = readl(&clock_manager_base->per_pll.perqspiclk);
492 		clock /= (reg + 1);
493 	}
494 
495 	return clock;
496 }
497 
498 unsigned int cm_get_spi_controller_clk_hz(void)
499 {
500 	u32 reg, clock = 0;
501 
502 	clock = cm_get_per_vco_clk_hz();
503 
504 	/* get the clock prior L4 SP divider (periph_base_clk) */
505 	reg = readl(&clock_manager_base->per_pll.perbaseclk);
506 	clock /= (reg + 1);
507 
508 	return clock;
509 }
510 
511 /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
512 int dw_spi_get_clk(struct udevice *bus, ulong *rate)
513 {
514 	*rate = cm_get_spi_controller_clk_hz();
515 
516 	return 0;
517 }
518 
519 void cm_print_clock_quick_summary(void)
520 {
521 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
522 	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
523 	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
524 	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
525 	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
526 	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
527 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
528 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
529 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
530 	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
531 }
532