1 /* 2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/clock_manager.h> 10 #include <wait_bit.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 static const struct socfpga_clock_manager *clock_manager_base = 15 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 16 17 /* 18 * function to write the bypass register which requires a poll of the 19 * busy bit 20 */ 21 static void cm_write_bypass(u32 val) 22 { 23 writel(val, &clock_manager_base->bypass); 24 cm_wait_for_fsm(); 25 } 26 27 /* function to write the ctrl register which requires a poll of the busy bit */ 28 static void cm_write_ctrl(u32 val) 29 { 30 writel(val, &clock_manager_base->ctrl); 31 cm_wait_for_fsm(); 32 } 33 34 /* function to write a clock register that has phase information */ 35 static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) 36 { 37 int ret; 38 39 /* poll until phase is zero */ 40 ret = wait_for_bit(__func__, (const u32 *)reg_address, mask, 41 false, 20000, false); 42 if (ret) 43 return ret; 44 45 writel(value, reg_address); 46 47 return wait_for_bit(__func__, (const u32 *)reg_address, mask, 48 false, 20000, false); 49 } 50 51 /* 52 * Setup clocks while making no assumptions about previous state of the clocks. 53 * 54 * Start by being paranoid and gate all sw managed clocks 55 * Put all plls in bypass 56 * Put all plls VCO registers back to reset value (bandgap power down). 57 * Put peripheral and main pll src to reset value to avoid glitch. 58 * Delay 5 us. 59 * Deassert bandgap power down and set numerator and denominator 60 * Start 7 us timer. 61 * set internal dividers 62 * Wait for 7 us timer. 63 * Enable plls 64 * Set external dividers while plls are locking 65 * Wait for pll lock 66 * Assert/deassert outreset all. 67 * Take all pll's out of bypass 68 * Clear safe mode 69 * set source main and peripheral clocks 70 * Ungate clocks 71 */ 72 73 int cm_basic_init(const struct cm_config * const cfg) 74 { 75 unsigned long end; 76 int ret; 77 78 /* Start by being paranoid and gate all sw managed clocks */ 79 80 /* 81 * We need to disable nandclk 82 * and then do another apb access before disabling 83 * gatting off the rest of the periperal clocks. 84 */ 85 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & 86 readl(&clock_manager_base->per_pll.en), 87 &clock_manager_base->per_pll.en); 88 89 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ 90 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | 91 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | 92 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | 93 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | 94 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | 95 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, 96 &clock_manager_base->main_pll.en); 97 98 writel(0, &clock_manager_base->sdr_pll.en); 99 100 /* now we can gate off the rest of the peripheral clocks */ 101 writel(0, &clock_manager_base->per_pll.en); 102 103 /* Put all plls in bypass */ 104 cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | 105 CLKMGR_BYPASS_MAINPLL); 106 107 /* Put all plls VCO registers back to reset value. */ 108 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & 109 ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, 110 &clock_manager_base->main_pll.vco); 111 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & 112 ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, 113 &clock_manager_base->per_pll.vco); 114 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & 115 ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, 116 &clock_manager_base->sdr_pll.vco); 117 118 /* 119 * The clocks to the flash devices and the L4_MAIN clocks can 120 * glitch when coming out of safe mode if their source values 121 * are different from their reset value. So the trick it to 122 * put them back to their reset state, and change input 123 * after exiting safe mode but before ungating the clocks. 124 */ 125 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, 126 &clock_manager_base->per_pll.src); 127 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, 128 &clock_manager_base->main_pll.l4src); 129 130 /* read back for the required 5 us delay. */ 131 readl(&clock_manager_base->main_pll.vco); 132 readl(&clock_manager_base->per_pll.vco); 133 readl(&clock_manager_base->sdr_pll.vco); 134 135 136 /* 137 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN 138 * with numerator and denominator. 139 */ 140 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); 141 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); 142 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); 143 144 /* 145 * Time starts here. Must wait 7 us from 146 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). 147 */ 148 end = timer_get_us() + 7; 149 150 /* main mpu */ 151 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); 152 153 /* altera group mpuclk */ 154 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); 155 156 /* main main clock */ 157 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); 158 159 /* main for dbg */ 160 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); 161 162 /* main for cfgs2fuser0clk */ 163 writel(cfg->cfg2fuser0clk, 164 &clock_manager_base->main_pll.cfgs2fuser0clk); 165 166 /* Peri emac0 50 MHz default to RMII */ 167 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); 168 169 /* Peri emac1 50 MHz default to RMII */ 170 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); 171 172 /* Peri QSPI */ 173 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); 174 175 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); 176 177 /* Peri pernandsdmmcclk */ 178 writel(cfg->mainnandsdmmcclk, 179 &clock_manager_base->main_pll.mainnandsdmmcclk); 180 181 writel(cfg->pernandsdmmcclk, 182 &clock_manager_base->per_pll.pernandsdmmcclk); 183 184 /* Peri perbaseclk */ 185 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); 186 187 /* Peri s2fuser1clk */ 188 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); 189 190 /* 7 us must have elapsed before we can enable the VCO */ 191 while (timer_get_us() < end) 192 ; 193 194 /* Enable vco */ 195 /* main pll vco */ 196 writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, 197 &clock_manager_base->main_pll.vco); 198 199 /* periferal pll */ 200 writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, 201 &clock_manager_base->per_pll.vco); 202 203 /* sdram pll vco */ 204 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, 205 &clock_manager_base->sdr_pll.vco); 206 207 /* L3 MP and L3 SP */ 208 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); 209 210 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); 211 212 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); 213 214 /* L4 MP, L4 SP, can0, and can1 */ 215 writel(cfg->perdiv, &clock_manager_base->per_pll.div); 216 217 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); 218 219 cm_wait_for_lock(LOCKED_MASK); 220 221 /* write the sdram clock counters before toggling outreset all */ 222 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, 223 &clock_manager_base->sdr_pll.ddrdqsclk); 224 225 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, 226 &clock_manager_base->sdr_pll.ddr2xdqsclk); 227 228 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, 229 &clock_manager_base->sdr_pll.ddrdqclk); 230 231 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, 232 &clock_manager_base->sdr_pll.s2fuser2clk); 233 234 /* 235 * after locking, but before taking out of bypass 236 * assert/deassert outresetall 237 */ 238 u32 mainvco = readl(&clock_manager_base->main_pll.vco); 239 240 /* assert main outresetall */ 241 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, 242 &clock_manager_base->main_pll.vco); 243 244 u32 periphvco = readl(&clock_manager_base->per_pll.vco); 245 246 /* assert pheriph outresetall */ 247 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, 248 &clock_manager_base->per_pll.vco); 249 250 /* assert sdram outresetall */ 251 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| 252 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, 253 &clock_manager_base->sdr_pll.vco); 254 255 /* deassert main outresetall */ 256 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, 257 &clock_manager_base->main_pll.vco); 258 259 /* deassert pheriph outresetall */ 260 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, 261 &clock_manager_base->per_pll.vco); 262 263 /* deassert sdram outresetall */ 264 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, 265 &clock_manager_base->sdr_pll.vco); 266 267 /* 268 * now that we've toggled outreset all, all the clocks 269 * are aligned nicely; so we can change any phase. 270 */ 271 ret = cm_write_with_phase(cfg->ddrdqsclk, 272 (u32)&clock_manager_base->sdr_pll.ddrdqsclk, 273 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); 274 if (ret) 275 return ret; 276 277 /* SDRAM DDR2XDQSCLK */ 278 ret = cm_write_with_phase(cfg->ddr2xdqsclk, 279 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, 280 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); 281 if (ret) 282 return ret; 283 284 ret = cm_write_with_phase(cfg->ddrdqclk, 285 (u32)&clock_manager_base->sdr_pll.ddrdqclk, 286 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); 287 if (ret) 288 return ret; 289 290 ret = cm_write_with_phase(cfg->s2fuser2clk, 291 (u32)&clock_manager_base->sdr_pll.s2fuser2clk, 292 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); 293 if (ret) 294 return ret; 295 296 /* Take all three PLLs out of bypass when safe mode is cleared. */ 297 cm_write_bypass(0); 298 299 /* clear safe mode */ 300 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); 301 302 /* 303 * now that safe mode is clear with clocks gated 304 * it safe to change the source mux for the flashes the the L4_MAIN 305 */ 306 writel(cfg->persrc, &clock_manager_base->per_pll.src); 307 writel(cfg->l4src, &clock_manager_base->main_pll.l4src); 308 309 /* Now ungate non-hw-managed clocks */ 310 writel(~0, &clock_manager_base->main_pll.en); 311 writel(~0, &clock_manager_base->per_pll.en); 312 writel(~0, &clock_manager_base->sdr_pll.en); 313 314 /* Clear the loss of lock bits (write 1 to clear) */ 315 writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | 316 CLKMGR_INTER_MAINPLLLOST_MASK, 317 &clock_manager_base->inter); 318 319 return 0; 320 } 321 322 static unsigned int cm_get_main_vco_clk_hz(void) 323 { 324 u32 reg, clock; 325 326 /* get the main VCO clock */ 327 reg = readl(&clock_manager_base->main_pll.vco); 328 clock = cm_get_osc_clk_hz(1); 329 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> 330 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; 331 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> 332 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; 333 334 return clock; 335 } 336 337 static unsigned int cm_get_per_vco_clk_hz(void) 338 { 339 u32 reg, clock = 0; 340 341 /* identify PER PLL clock source */ 342 reg = readl(&clock_manager_base->per_pll.vco); 343 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> 344 CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; 345 if (reg == CLKMGR_VCO_SSRC_EOSC1) 346 clock = cm_get_osc_clk_hz(1); 347 else if (reg == CLKMGR_VCO_SSRC_EOSC2) 348 clock = cm_get_osc_clk_hz(2); 349 else if (reg == CLKMGR_VCO_SSRC_F2S) 350 clock = cm_get_f2s_per_ref_clk_hz(); 351 352 /* get the PER VCO clock */ 353 reg = readl(&clock_manager_base->per_pll.vco); 354 clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> 355 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; 356 clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> 357 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; 358 359 return clock; 360 } 361 362 unsigned long cm_get_mpu_clk_hz(void) 363 { 364 u32 reg, clock; 365 366 clock = cm_get_main_vco_clk_hz(); 367 368 /* get the MPU clock */ 369 reg = readl(&clock_manager_base->altera.mpuclk); 370 clock /= (reg + 1); 371 reg = readl(&clock_manager_base->main_pll.mpuclk); 372 clock /= (reg + 1); 373 return clock; 374 } 375 376 unsigned long cm_get_sdram_clk_hz(void) 377 { 378 u32 reg, clock = 0; 379 380 /* identify SDRAM PLL clock source */ 381 reg = readl(&clock_manager_base->sdr_pll.vco); 382 reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> 383 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; 384 if (reg == CLKMGR_VCO_SSRC_EOSC1) 385 clock = cm_get_osc_clk_hz(1); 386 else if (reg == CLKMGR_VCO_SSRC_EOSC2) 387 clock = cm_get_osc_clk_hz(2); 388 else if (reg == CLKMGR_VCO_SSRC_F2S) 389 clock = cm_get_f2s_sdr_ref_clk_hz(); 390 391 /* get the SDRAM VCO clock */ 392 reg = readl(&clock_manager_base->sdr_pll.vco); 393 clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> 394 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; 395 clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> 396 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; 397 398 /* get the SDRAM (DDR_DQS) clock */ 399 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); 400 reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> 401 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; 402 clock /= (reg + 1); 403 404 return clock; 405 } 406 407 unsigned int cm_get_l4_sp_clk_hz(void) 408 { 409 u32 reg, clock = 0; 410 411 /* identify the source of L4 SP clock */ 412 reg = readl(&clock_manager_base->main_pll.l4src); 413 reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> 414 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; 415 416 if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { 417 clock = cm_get_main_vco_clk_hz(); 418 419 /* get the clock prior L4 SP divider (main clk) */ 420 reg = readl(&clock_manager_base->altera.mainclk); 421 clock /= (reg + 1); 422 reg = readl(&clock_manager_base->main_pll.mainclk); 423 clock /= (reg + 1); 424 } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { 425 clock = cm_get_per_vco_clk_hz(); 426 427 /* get the clock prior L4 SP divider (periph_base_clk) */ 428 reg = readl(&clock_manager_base->per_pll.perbaseclk); 429 clock /= (reg + 1); 430 } 431 432 /* get the L4 SP clock which supplied to UART */ 433 reg = readl(&clock_manager_base->main_pll.maindiv); 434 reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> 435 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; 436 clock = clock / (1 << reg); 437 438 return clock; 439 } 440 441 unsigned int cm_get_mmc_controller_clk_hz(void) 442 { 443 u32 reg, clock = 0; 444 445 /* identify the source of MMC clock */ 446 reg = readl(&clock_manager_base->per_pll.src); 447 reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> 448 CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; 449 450 if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { 451 clock = cm_get_f2s_per_ref_clk_hz(); 452 } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { 453 clock = cm_get_main_vco_clk_hz(); 454 455 /* get the SDMMC clock */ 456 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); 457 clock /= (reg + 1); 458 } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { 459 clock = cm_get_per_vco_clk_hz(); 460 461 /* get the SDMMC clock */ 462 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); 463 clock /= (reg + 1); 464 } 465 466 /* further divide by 4 as we have fixed divider at wrapper */ 467 clock /= 4; 468 return clock; 469 } 470 471 unsigned int cm_get_qspi_controller_clk_hz(void) 472 { 473 u32 reg, clock = 0; 474 475 /* identify the source of QSPI clock */ 476 reg = readl(&clock_manager_base->per_pll.src); 477 reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> 478 CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; 479 480 if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { 481 clock = cm_get_f2s_per_ref_clk_hz(); 482 } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { 483 clock = cm_get_main_vco_clk_hz(); 484 485 /* get the qspi clock */ 486 reg = readl(&clock_manager_base->main_pll.mainqspiclk); 487 clock /= (reg + 1); 488 } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { 489 clock = cm_get_per_vco_clk_hz(); 490 491 /* get the qspi clock */ 492 reg = readl(&clock_manager_base->per_pll.perqspiclk); 493 clock /= (reg + 1); 494 } 495 496 return clock; 497 } 498 499 unsigned int cm_get_spi_controller_clk_hz(void) 500 { 501 u32 reg, clock = 0; 502 503 clock = cm_get_per_vco_clk_hz(); 504 505 /* get the clock prior L4 SP divider (periph_base_clk) */ 506 reg = readl(&clock_manager_base->per_pll.perbaseclk); 507 clock /= (reg + 1); 508 509 return clock; 510 } 511 512 void cm_print_clock_quick_summary(void) 513 { 514 printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); 515 printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); 516 printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000); 517 printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000); 518 printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000); 519 printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000); 520 printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); 521 printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); 522 printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); 523 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); 524 } 525