1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <dm.h>
9 #include <asm/arch/clock_manager.h>
10 #include <wait_bit.h>
11 
12 static const struct socfpga_clock_manager *clock_manager_base =
13 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
14 
15 /*
16  * function to write the bypass register which requires a poll of the
17  * busy bit
18  */
19 static void cm_write_bypass(u32 val)
20 {
21 	writel(val, &clock_manager_base->bypass);
22 	cm_wait_for_fsm();
23 }
24 
25 /* function to write the ctrl register which requires a poll of the busy bit */
26 static void cm_write_ctrl(u32 val)
27 {
28 	writel(val, &clock_manager_base->ctrl);
29 	cm_wait_for_fsm();
30 }
31 
32 /* function to write a clock register that has phase information */
33 static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
34 {
35 	int ret;
36 
37 	/* poll until phase is zero */
38 	ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
39 	if (ret)
40 		return ret;
41 
42 	writel(value, reg_address);
43 
44 	return wait_for_bit_le32(reg_address, mask, false, 20000, false);
45 }
46 
47 /*
48  * Setup clocks while making no assumptions about previous state of the clocks.
49  *
50  * Start by being paranoid and gate all sw managed clocks
51  * Put all plls in bypass
52  * Put all plls VCO registers back to reset value (bandgap power down).
53  * Put peripheral and main pll src to reset value to avoid glitch.
54  * Delay 5 us.
55  * Deassert bandgap power down and set numerator and denominator
56  * Start 7 us timer.
57  * set internal dividers
58  * Wait for 7 us timer.
59  * Enable plls
60  * Set external dividers while plls are locking
61  * Wait for pll lock
62  * Assert/deassert outreset all.
63  * Take all pll's out of bypass
64  * Clear safe mode
65  * set source main and peripheral clocks
66  * Ungate clocks
67  */
68 
69 int cm_basic_init(const struct cm_config * const cfg)
70 {
71 	unsigned long end;
72 	int ret;
73 
74 	/* Start by being paranoid and gate all sw managed clocks */
75 
76 	/*
77 	 * We need to disable nandclk
78 	 * and then do another apb access before disabling
79 	 * gatting off the rest of the periperal clocks.
80 	 */
81 	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
82 		readl(&clock_manager_base->per_pll.en),
83 		&clock_manager_base->per_pll.en);
84 
85 	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
86 	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
87 		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
88 		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
89 		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
90 		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
91 		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
92 		&clock_manager_base->main_pll.en);
93 
94 	writel(0, &clock_manager_base->sdr_pll.en);
95 
96 	/* now we can gate off the rest of the peripheral clocks */
97 	writel(0, &clock_manager_base->per_pll.en);
98 
99 	/* Put all plls in bypass */
100 	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
101 			CLKMGR_BYPASS_MAINPLL);
102 
103 	/* Put all plls VCO registers back to reset value. */
104 	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
105 	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
106 	       &clock_manager_base->main_pll.vco);
107 	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
108 	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
109 	       &clock_manager_base->per_pll.vco);
110 	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
111 	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
112 	       &clock_manager_base->sdr_pll.vco);
113 
114 	/*
115 	 * The clocks to the flash devices and the L4_MAIN clocks can
116 	 * glitch when coming out of safe mode if their source values
117 	 * are different from their reset value.  So the trick it to
118 	 * put them back to their reset state, and change input
119 	 * after exiting safe mode but before ungating the clocks.
120 	 */
121 	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
122 	       &clock_manager_base->per_pll.src);
123 	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
124 	       &clock_manager_base->main_pll.l4src);
125 
126 	/* read back for the required 5 us delay. */
127 	readl(&clock_manager_base->main_pll.vco);
128 	readl(&clock_manager_base->per_pll.vco);
129 	readl(&clock_manager_base->sdr_pll.vco);
130 
131 
132 	/*
133 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
134 	 * with numerator and denominator.
135 	 */
136 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
137 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
138 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
139 
140 	/*
141 	 * Time starts here. Must wait 7 us from
142 	 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
143 	 */
144 	end = timer_get_us() + 7;
145 
146 	/* main mpu */
147 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
148 
149 	/* altera group mpuclk */
150 	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
151 
152 	/* main main clock */
153 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
154 
155 	/* main for dbg */
156 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
157 
158 	/* main for cfgs2fuser0clk */
159 	writel(cfg->cfg2fuser0clk,
160 	       &clock_manager_base->main_pll.cfgs2fuser0clk);
161 
162 	/* Peri emac0 50 MHz default to RMII */
163 	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
164 
165 	/* Peri emac1 50 MHz default to RMII */
166 	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
167 
168 	/* Peri QSPI */
169 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
170 
171 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
172 
173 	/* Peri pernandsdmmcclk */
174 	writel(cfg->mainnandsdmmcclk,
175 	       &clock_manager_base->main_pll.mainnandsdmmcclk);
176 
177 	writel(cfg->pernandsdmmcclk,
178 	       &clock_manager_base->per_pll.pernandsdmmcclk);
179 
180 	/* Peri perbaseclk */
181 	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
182 
183 	/* Peri s2fuser1clk */
184 	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
185 
186 	/* 7 us must have elapsed before we can enable the VCO */
187 	while (timer_get_us() < end)
188 		;
189 
190 	/* Enable vco */
191 	/* main pll vco */
192 	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
193 	       &clock_manager_base->main_pll.vco);
194 
195 	/* periferal pll */
196 	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
197 	       &clock_manager_base->per_pll.vco);
198 
199 	/* sdram pll vco */
200 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
201 	       &clock_manager_base->sdr_pll.vco);
202 
203 	/* L3 MP and L3 SP */
204 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
205 
206 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
207 
208 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
209 
210 	/* L4 MP, L4 SP, can0, and can1 */
211 	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
212 
213 	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
214 
215 	cm_wait_for_lock(LOCKED_MASK);
216 
217 	/* write the sdram clock counters before toggling outreset all */
218 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
219 	       &clock_manager_base->sdr_pll.ddrdqsclk);
220 
221 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
222 	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
223 
224 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
225 	       &clock_manager_base->sdr_pll.ddrdqclk);
226 
227 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
228 	       &clock_manager_base->sdr_pll.s2fuser2clk);
229 
230 	/*
231 	 * after locking, but before taking out of bypass
232 	 * assert/deassert outresetall
233 	 */
234 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);
235 
236 	/* assert main outresetall */
237 	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
238 	       &clock_manager_base->main_pll.vco);
239 
240 	u32 periphvco = readl(&clock_manager_base->per_pll.vco);
241 
242 	/* assert pheriph outresetall */
243 	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
244 	       &clock_manager_base->per_pll.vco);
245 
246 	/* assert sdram outresetall */
247 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
248 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
249 		&clock_manager_base->sdr_pll.vco);
250 
251 	/* deassert main outresetall */
252 	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
253 	       &clock_manager_base->main_pll.vco);
254 
255 	/* deassert pheriph outresetall */
256 	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
257 	       &clock_manager_base->per_pll.vco);
258 
259 	/* deassert sdram outresetall */
260 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
261 	       &clock_manager_base->sdr_pll.vco);
262 
263 	/*
264 	 * now that we've toggled outreset all, all the clocks
265 	 * are aligned nicely; so we can change any phase.
266 	 */
267 	ret = cm_write_with_phase(cfg->ddrdqsclk,
268 				  &clock_manager_base->sdr_pll.ddrdqsclk,
269 				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
270 	if (ret)
271 		return ret;
272 
273 	/* SDRAM DDR2XDQSCLK */
274 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
275 				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
276 				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
277 	if (ret)
278 		return ret;
279 
280 	ret = cm_write_with_phase(cfg->ddrdqclk,
281 				  &clock_manager_base->sdr_pll.ddrdqclk,
282 				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
283 	if (ret)
284 		return ret;
285 
286 	ret = cm_write_with_phase(cfg->s2fuser2clk,
287 				  &clock_manager_base->sdr_pll.s2fuser2clk,
288 				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
289 	if (ret)
290 		return ret;
291 
292 	/* Take all three PLLs out of bypass when safe mode is cleared. */
293 	cm_write_bypass(0);
294 
295 	/* clear safe mode */
296 	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
297 
298 	/*
299 	 * now that safe mode is clear with clocks gated
300 	 * it safe to change the source mux for the flashes the the L4_MAIN
301 	 */
302 	writel(cfg->persrc, &clock_manager_base->per_pll.src);
303 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
304 
305 	/* Now ungate non-hw-managed clocks */
306 	writel(~0, &clock_manager_base->main_pll.en);
307 	writel(~0, &clock_manager_base->per_pll.en);
308 	writel(~0, &clock_manager_base->sdr_pll.en);
309 
310 	/* Clear the loss of lock bits (write 1 to clear) */
311 	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
312 	       CLKMGR_INTER_MAINPLLLOST_MASK,
313 	       &clock_manager_base->inter);
314 
315 	return 0;
316 }
317 
318 static unsigned int cm_get_main_vco_clk_hz(void)
319 {
320 	u32 reg, clock;
321 
322 	/* get the main VCO clock */
323 	reg = readl(&clock_manager_base->main_pll.vco);
324 	clock = cm_get_osc_clk_hz(1);
325 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
326 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
327 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
328 		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
329 
330 	return clock;
331 }
332 
333 static unsigned int cm_get_per_vco_clk_hz(void)
334 {
335 	u32 reg, clock = 0;
336 
337 	/* identify PER PLL clock source */
338 	reg = readl(&clock_manager_base->per_pll.vco);
339 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
340 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
341 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
342 		clock = cm_get_osc_clk_hz(1);
343 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
344 		clock = cm_get_osc_clk_hz(2);
345 	else if (reg == CLKMGR_VCO_SSRC_F2S)
346 		clock = cm_get_f2s_per_ref_clk_hz();
347 
348 	/* get the PER VCO clock */
349 	reg = readl(&clock_manager_base->per_pll.vco);
350 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
351 		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
352 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
353 		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
354 
355 	return clock;
356 }
357 
358 unsigned long cm_get_mpu_clk_hz(void)
359 {
360 	u32 reg, clock;
361 
362 	clock = cm_get_main_vco_clk_hz();
363 
364 	/* get the MPU clock */
365 	reg = readl(&clock_manager_base->altera.mpuclk);
366 	clock /= (reg + 1);
367 	reg = readl(&clock_manager_base->main_pll.mpuclk);
368 	clock /= (reg + 1);
369 	return clock;
370 }
371 
372 unsigned long cm_get_sdram_clk_hz(void)
373 {
374 	u32 reg, clock = 0;
375 
376 	/* identify SDRAM PLL clock source */
377 	reg = readl(&clock_manager_base->sdr_pll.vco);
378 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
379 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
380 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
381 		clock = cm_get_osc_clk_hz(1);
382 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
383 		clock = cm_get_osc_clk_hz(2);
384 	else if (reg == CLKMGR_VCO_SSRC_F2S)
385 		clock = cm_get_f2s_sdr_ref_clk_hz();
386 
387 	/* get the SDRAM VCO clock */
388 	reg = readl(&clock_manager_base->sdr_pll.vco);
389 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
390 		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
391 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
392 		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
393 
394 	/* get the SDRAM (DDR_DQS) clock */
395 	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
396 	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
397 	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
398 	clock /= (reg + 1);
399 
400 	return clock;
401 }
402 
403 unsigned int cm_get_l4_sp_clk_hz(void)
404 {
405 	u32 reg, clock = 0;
406 
407 	/* identify the source of L4 SP clock */
408 	reg = readl(&clock_manager_base->main_pll.l4src);
409 	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
410 	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
411 
412 	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
413 		clock = cm_get_main_vco_clk_hz();
414 
415 		/* get the clock prior L4 SP divider (main clk) */
416 		reg = readl(&clock_manager_base->altera.mainclk);
417 		clock /= (reg + 1);
418 		reg = readl(&clock_manager_base->main_pll.mainclk);
419 		clock /= (reg + 1);
420 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
421 		clock = cm_get_per_vco_clk_hz();
422 
423 		/* get the clock prior L4 SP divider (periph_base_clk) */
424 		reg = readl(&clock_manager_base->per_pll.perbaseclk);
425 		clock /= (reg + 1);
426 	}
427 
428 	/* get the L4 SP clock which supplied to UART */
429 	reg = readl(&clock_manager_base->main_pll.maindiv);
430 	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
431 	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
432 	clock = clock / (1 << reg);
433 
434 	return clock;
435 }
436 
437 unsigned int cm_get_mmc_controller_clk_hz(void)
438 {
439 	u32 reg, clock = 0;
440 
441 	/* identify the source of MMC clock */
442 	reg = readl(&clock_manager_base->per_pll.src);
443 	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
444 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
445 
446 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
447 		clock = cm_get_f2s_per_ref_clk_hz();
448 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
449 		clock = cm_get_main_vco_clk_hz();
450 
451 		/* get the SDMMC clock */
452 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
453 		clock /= (reg + 1);
454 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
455 		clock = cm_get_per_vco_clk_hz();
456 
457 		/* get the SDMMC clock */
458 		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
459 		clock /= (reg + 1);
460 	}
461 
462 	/* further divide by 4 as we have fixed divider at wrapper */
463 	clock /= 4;
464 	return clock;
465 }
466 
467 unsigned int cm_get_qspi_controller_clk_hz(void)
468 {
469 	u32 reg, clock = 0;
470 
471 	/* identify the source of QSPI clock */
472 	reg = readl(&clock_manager_base->per_pll.src);
473 	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
474 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
475 
476 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
477 		clock = cm_get_f2s_per_ref_clk_hz();
478 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
479 		clock = cm_get_main_vco_clk_hz();
480 
481 		/* get the qspi clock */
482 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
483 		clock /= (reg + 1);
484 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
485 		clock = cm_get_per_vco_clk_hz();
486 
487 		/* get the qspi clock */
488 		reg = readl(&clock_manager_base->per_pll.perqspiclk);
489 		clock /= (reg + 1);
490 	}
491 
492 	return clock;
493 }
494 
495 unsigned int cm_get_spi_controller_clk_hz(void)
496 {
497 	u32 reg, clock = 0;
498 
499 	clock = cm_get_per_vco_clk_hz();
500 
501 	/* get the clock prior L4 SP divider (periph_base_clk) */
502 	reg = readl(&clock_manager_base->per_pll.perbaseclk);
503 	clock /= (reg + 1);
504 
505 	return clock;
506 }
507 
508 /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
509 int dw_spi_get_clk(struct udevice *bus, ulong *rate)
510 {
511 	*rate = cm_get_spi_controller_clk_hz();
512 
513 	return 0;
514 }
515 
516 void cm_print_clock_quick_summary(void)
517 {
518 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
519 	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
520 	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
521 	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
522 	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
523 	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
524 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
525 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
526 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
527 	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
528 }
529