183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2177ba1f9SLey Foon Tan /* 3177ba1f9SLey Foon Tan * Copyright (C) 2016-2017 Intel Corporation 4177ba1f9SLey Foon Tan */ 5177ba1f9SLey Foon Tan 6177ba1f9SLey Foon Tan #include <common.h> 7177ba1f9SLey Foon Tan #include <fdtdec.h> 8177ba1f9SLey Foon Tan #include <asm/io.h> 921143ce1SEugeniy Paltsev #include <dm.h> 10934aec71SMarek Vasut #include <clk.h> 11934aec71SMarek Vasut #include <dm/device-internal.h> 12177ba1f9SLey Foon Tan #include <asm/arch/clock_manager.h> 13177ba1f9SLey Foon Tan 14480f7f9cSMarek Vasut static const struct socfpga_clock_manager *clock_manager_base = 15480f7f9cSMarek Vasut (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 16480f7f9cSMarek Vasut 17177ba1f9SLey Foon Tan static u32 eosc1_hz; 18177ba1f9SLey Foon Tan static u32 cb_intosc_hz; 19177ba1f9SLey Foon Tan static u32 f2s_free_hz; 20177ba1f9SLey Foon Tan 21177ba1f9SLey Foon Tan struct mainpll_cfg { 22177ba1f9SLey Foon Tan u32 vco0_psrc; 23177ba1f9SLey Foon Tan u32 vco1_denom; 24177ba1f9SLey Foon Tan u32 vco1_numer; 25177ba1f9SLey Foon Tan u32 mpuclk; 26177ba1f9SLey Foon Tan u32 mpuclk_cnt; 27177ba1f9SLey Foon Tan u32 mpuclk_src; 28177ba1f9SLey Foon Tan u32 nocclk; 29177ba1f9SLey Foon Tan u32 nocclk_cnt; 30177ba1f9SLey Foon Tan u32 nocclk_src; 31177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 32177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 33177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 34177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 35177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 36177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 37177ba1f9SLey Foon Tan u32 cntr7clk_src; 38177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 39177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 40177ba1f9SLey Foon Tan u32 cntr9clk_src; 41177ba1f9SLey Foon Tan u32 cntr15clk_cnt; 42177ba1f9SLey Foon Tan u32 nocdiv_l4mainclk; 43177ba1f9SLey Foon Tan u32 nocdiv_l4mpclk; 44177ba1f9SLey Foon Tan u32 nocdiv_l4spclk; 45177ba1f9SLey Foon Tan u32 nocdiv_csatclk; 46177ba1f9SLey Foon Tan u32 nocdiv_cstraceclk; 47177ba1f9SLey Foon Tan u32 nocdiv_cspdbclk; 48177ba1f9SLey Foon Tan }; 49177ba1f9SLey Foon Tan 50177ba1f9SLey Foon Tan struct perpll_cfg { 51177ba1f9SLey Foon Tan u32 vco0_psrc; 52177ba1f9SLey Foon Tan u32 vco1_denom; 53177ba1f9SLey Foon Tan u32 vco1_numer; 54177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 55177ba1f9SLey Foon Tan u32 cntr2clk_src; 56177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 57177ba1f9SLey Foon Tan u32 cntr3clk_src; 58177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 59177ba1f9SLey Foon Tan u32 cntr4clk_src; 60177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 61177ba1f9SLey Foon Tan u32 cntr5clk_src; 62177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 63177ba1f9SLey Foon Tan u32 cntr6clk_src; 64177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 65177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 66177ba1f9SLey Foon Tan u32 cntr8clk_src; 67177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 68480f7f9cSMarek Vasut u32 cntr9clk_src; 69177ba1f9SLey Foon Tan u32 emacctl_emac0sel; 70177ba1f9SLey Foon Tan u32 emacctl_emac1sel; 71177ba1f9SLey Foon Tan u32 emacctl_emac2sel; 72177ba1f9SLey Foon Tan u32 gpiodiv_gpiodbclk; 73177ba1f9SLey Foon Tan }; 74177ba1f9SLey Foon Tan 75480f7f9cSMarek Vasut struct strtou32 { 76480f7f9cSMarek Vasut const char *str; 77480f7f9cSMarek Vasut const u32 val; 78177ba1f9SLey Foon Tan }; 79177ba1f9SLey Foon Tan 80480f7f9cSMarek Vasut static const struct strtou32 mainpll_cfg_tab[] = { 81480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, 82480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, 83480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, 84480f7f9cSMarek Vasut { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, 85480f7f9cSMarek Vasut { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, 86480f7f9cSMarek Vasut { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, 87480f7f9cSMarek Vasut { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) }, 88480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) }, 89480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) }, 90480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) }, 91480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) }, 92480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) }, 93480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) }, 94480f7f9cSMarek Vasut { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) }, 95480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) }, 96480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) }, 97480f7f9cSMarek Vasut { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) }, 98480f7f9cSMarek Vasut { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) }, 99480f7f9cSMarek Vasut { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) }, 100480f7f9cSMarek Vasut { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) }, 101480f7f9cSMarek Vasut { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) }, 102480f7f9cSMarek Vasut { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) }, 103480f7f9cSMarek Vasut { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) }, 104480f7f9cSMarek Vasut { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) }, 105480f7f9cSMarek Vasut }; 106177ba1f9SLey Foon Tan 107480f7f9cSMarek Vasut static const struct strtou32 perpll_cfg_tab[] = { 108480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) }, 109480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) }, 110480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) }, 111480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) }, 112480f7f9cSMarek Vasut { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) }, 113480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) }, 114480f7f9cSMarek Vasut { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) }, 115480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) }, 116480f7f9cSMarek Vasut { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) }, 117480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) }, 118480f7f9cSMarek Vasut { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) }, 119480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) }, 120480f7f9cSMarek Vasut { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) }, 121480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) }, 122480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) }, 123480f7f9cSMarek Vasut { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) }, 124480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) }, 125480f7f9cSMarek Vasut { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) }, 126480f7f9cSMarek Vasut { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) }, 127480f7f9cSMarek Vasut { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) }, 128480f7f9cSMarek Vasut { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) }, 129480f7f9cSMarek Vasut }; 130480f7f9cSMarek Vasut 131480f7f9cSMarek Vasut static const struct strtou32 alteragrp_cfg_tab[] = { 132480f7f9cSMarek Vasut { "nocclk", offsetof(struct mainpll_cfg, nocclk) }, 133480f7f9cSMarek Vasut { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) }, 134480f7f9cSMarek Vasut }; 135480f7f9cSMarek Vasut 136480f7f9cSMarek Vasut struct strtopu32 { 137480f7f9cSMarek Vasut const char *str; 138480f7f9cSMarek Vasut u32 *p; 139480f7f9cSMarek Vasut }; 140480f7f9cSMarek Vasut 141480f7f9cSMarek Vasut const struct strtopu32 dt_to_val[] = { 142934aec71SMarek Vasut { "altera_arria10_hps_eosc1", &eosc1_hz }, 143934aec71SMarek Vasut { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, 144934aec71SMarek Vasut { "altera_arria10_hps_f2h_free", &f2s_free_hz }, 145480f7f9cSMarek Vasut }; 146480f7f9cSMarek Vasut 147480f7f9cSMarek Vasut static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, 148480f7f9cSMarek Vasut int cfg_tab_len, void *cfg) 149177ba1f9SLey Foon Tan { 150480f7f9cSMarek Vasut int i; 151480f7f9cSMarek Vasut u32 val; 152480f7f9cSMarek Vasut 153480f7f9cSMarek Vasut for (i = 0; i < cfg_tab_len; i++) { 154480f7f9cSMarek Vasut if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) { 155177ba1f9SLey Foon Tan /* could not find required property */ 156177ba1f9SLey Foon Tan return -EINVAL; 157177ba1f9SLey Foon Tan } 158480f7f9cSMarek Vasut *(u32 *)(cfg + cfg_tab[i].val) = val; 159480f7f9cSMarek Vasut } 160177ba1f9SLey Foon Tan 161177ba1f9SLey Foon Tan return 0; 162177ba1f9SLey Foon Tan } 163177ba1f9SLey Foon Tan 164934aec71SMarek Vasut static int of_get_input_clks(const void *blob) 165177ba1f9SLey Foon Tan { 166934aec71SMarek Vasut struct udevice *dev; 167934aec71SMarek Vasut struct clk clk; 168934aec71SMarek Vasut int i, ret; 169177ba1f9SLey Foon Tan 170480f7f9cSMarek Vasut for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { 171934aec71SMarek Vasut memset(&clk, 0, sizeof(clk)); 172480f7f9cSMarek Vasut 173934aec71SMarek Vasut ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, 174934aec71SMarek Vasut &dev); 175934aec71SMarek Vasut if (ret) 176934aec71SMarek Vasut return ret; 177480f7f9cSMarek Vasut 178934aec71SMarek Vasut ret = clk_request(dev, &clk); 179934aec71SMarek Vasut if (ret) 180934aec71SMarek Vasut return ret; 181934aec71SMarek Vasut 182934aec71SMarek Vasut *dt_to_val[i].p = clk_get_rate(&clk); 183480f7f9cSMarek Vasut } 184934aec71SMarek Vasut 185934aec71SMarek Vasut return 0; 186177ba1f9SLey Foon Tan } 187177ba1f9SLey Foon Tan 188177ba1f9SLey Foon Tan static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, 189480f7f9cSMarek Vasut struct perpll_cfg *per_cfg) 190177ba1f9SLey Foon Tan { 191934aec71SMarek Vasut int ret, node, child, len; 192177ba1f9SLey Foon Tan const char *node_name; 193177ba1f9SLey Foon Tan 194934aec71SMarek Vasut ret = of_get_input_clks(blob); 195934aec71SMarek Vasut if (ret) 196934aec71SMarek Vasut return ret; 197480f7f9cSMarek Vasut 198480f7f9cSMarek Vasut node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); 199480f7f9cSMarek Vasut 200177ba1f9SLey Foon Tan if (node < 0) 201177ba1f9SLey Foon Tan return -EINVAL; 202177ba1f9SLey Foon Tan 203177ba1f9SLey Foon Tan child = fdt_first_subnode(blob, node); 204177ba1f9SLey Foon Tan 205177ba1f9SLey Foon Tan if (child < 0) 206177ba1f9SLey Foon Tan return -EINVAL; 207177ba1f9SLey Foon Tan 208177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 209177ba1f9SLey Foon Tan 210177ba1f9SLey Foon Tan while (node_name) { 211480f7f9cSMarek Vasut if (!strcmp(node_name, "mainpll")) { 212480f7f9cSMarek Vasut if (of_to_struct(blob, child, mainpll_cfg_tab, 213480f7f9cSMarek Vasut ARRAY_SIZE(mainpll_cfg_tab), main_cfg)) 214177ba1f9SLey Foon Tan return -EINVAL; 215480f7f9cSMarek Vasut } else if (!strcmp(node_name, "perpll")) { 216480f7f9cSMarek Vasut if (of_to_struct(blob, child, perpll_cfg_tab, 217480f7f9cSMarek Vasut ARRAY_SIZE(perpll_cfg_tab), per_cfg)) 218177ba1f9SLey Foon Tan return -EINVAL; 219480f7f9cSMarek Vasut } else if (!strcmp(node_name, "alteragrp")) { 220480f7f9cSMarek Vasut if (of_to_struct(blob, child, alteragrp_cfg_tab, 221480f7f9cSMarek Vasut ARRAY_SIZE(alteragrp_cfg_tab), main_cfg)) 222177ba1f9SLey Foon Tan return -EINVAL; 223177ba1f9SLey Foon Tan } 224177ba1f9SLey Foon Tan child = fdt_next_subnode(blob, child); 225177ba1f9SLey Foon Tan 226177ba1f9SLey Foon Tan if (child < 0) 227177ba1f9SLey Foon Tan break; 228177ba1f9SLey Foon Tan 229177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 230177ba1f9SLey Foon Tan } 231177ba1f9SLey Foon Tan 232177ba1f9SLey Foon Tan return 0; 233177ba1f9SLey Foon Tan } 234177ba1f9SLey Foon Tan 235177ba1f9SLey Foon Tan /* calculate the intended main VCO frequency based on handoff */ 236177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_main_vco_clk_hz 237177ba1f9SLey Foon Tan (struct mainpll_cfg *main_cfg) 238177ba1f9SLey Foon Tan { 239177ba1f9SLey Foon Tan unsigned int clk_hz; 240177ba1f9SLey Foon Tan 241177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 242177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 243177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 244177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 245177ba1f9SLey Foon Tan break; 246177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 247177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 248177ba1f9SLey Foon Tan break; 249177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 250177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 251177ba1f9SLey Foon Tan break; 252177ba1f9SLey Foon Tan default: 253177ba1f9SLey Foon Tan return 0; 254177ba1f9SLey Foon Tan } 255177ba1f9SLey Foon Tan 256177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 257177ba1f9SLey Foon Tan clk_hz /= 1 + main_cfg->vco1_denom; 258177ba1f9SLey Foon Tan clk_hz *= 1 + main_cfg->vco1_numer; 259177ba1f9SLey Foon Tan 260177ba1f9SLey Foon Tan return clk_hz; 261177ba1f9SLey Foon Tan } 262177ba1f9SLey Foon Tan 263177ba1f9SLey Foon Tan /* calculate the intended periph VCO frequency based on handoff */ 264177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_periph_vco_clk_hz( 265177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 266177ba1f9SLey Foon Tan { 267177ba1f9SLey Foon Tan unsigned int clk_hz; 268177ba1f9SLey Foon Tan 269177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ 270177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 271177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 272177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 273177ba1f9SLey Foon Tan break; 274177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 275177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 276177ba1f9SLey Foon Tan break; 277177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 278177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 279177ba1f9SLey Foon Tan break; 280177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 281177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 282177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 283177ba1f9SLey Foon Tan break; 284177ba1f9SLey Foon Tan default: 285177ba1f9SLey Foon Tan return 0; 286177ba1f9SLey Foon Tan } 287177ba1f9SLey Foon Tan 288177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 289177ba1f9SLey Foon Tan clk_hz /= 1 + per_cfg->vco1_denom; 290177ba1f9SLey Foon Tan clk_hz *= 1 + per_cfg->vco1_numer; 291177ba1f9SLey Foon Tan 292177ba1f9SLey Foon Tan return clk_hz; 293177ba1f9SLey Foon Tan } 294177ba1f9SLey Foon Tan 295177ba1f9SLey Foon Tan /* calculate the intended MPU clock frequency based on handoff */ 296177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, 297177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 298177ba1f9SLey Foon Tan { 299177ba1f9SLey Foon Tan unsigned int clk_hz; 300177ba1f9SLey Foon Tan 301177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 302177ba1f9SLey Foon Tan switch (main_cfg->mpuclk_src) { 303177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 304177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 305177ba1f9SLey Foon Tan clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) 306177ba1f9SLey Foon Tan + 1; 307177ba1f9SLey Foon Tan break; 308177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 309177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 310177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->mpuclk >> 311177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 312177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 313177ba1f9SLey Foon Tan break; 314177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 315177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 316177ba1f9SLey Foon Tan break; 317177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 318177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 319177ba1f9SLey Foon Tan break; 320177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 321177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 322177ba1f9SLey Foon Tan break; 323177ba1f9SLey Foon Tan default: 324177ba1f9SLey Foon Tan return 0; 325177ba1f9SLey Foon Tan } 326177ba1f9SLey Foon Tan 327177ba1f9SLey Foon Tan clk_hz /= main_cfg->mpuclk_cnt + 1; 328177ba1f9SLey Foon Tan return clk_hz; 329177ba1f9SLey Foon Tan } 330177ba1f9SLey Foon Tan 331177ba1f9SLey Foon Tan /* calculate the intended NOC clock frequency based on handoff */ 332177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, 333177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 334177ba1f9SLey Foon Tan { 335177ba1f9SLey Foon Tan unsigned int clk_hz; 336177ba1f9SLey Foon Tan 337177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 338177ba1f9SLey Foon Tan switch (main_cfg->nocclk_src) { 339177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: 340177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 341177ba1f9SLey Foon Tan clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) 342177ba1f9SLey Foon Tan + 1; 343177ba1f9SLey Foon Tan break; 344177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: 345177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 346177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->nocclk >> 347177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 348177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; 349177ba1f9SLey Foon Tan break; 350177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: 351177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 352177ba1f9SLey Foon Tan break; 353177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: 354177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 355177ba1f9SLey Foon Tan break; 356177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: 357177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 358177ba1f9SLey Foon Tan break; 359177ba1f9SLey Foon Tan default: 360177ba1f9SLey Foon Tan return 0; 361177ba1f9SLey Foon Tan } 362177ba1f9SLey Foon Tan 363177ba1f9SLey Foon Tan clk_hz /= main_cfg->nocclk_cnt + 1; 364177ba1f9SLey Foon Tan return clk_hz; 365177ba1f9SLey Foon Tan } 366177ba1f9SLey Foon Tan 367177ba1f9SLey Foon Tan /* return 1 if PLL ramp is required */ 368177ba1f9SLey Foon Tan static int cm_is_pll_ramp_required(int main0periph1, 369177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 370177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 371177ba1f9SLey Foon Tan { 372177ba1f9SLey Foon Tan /* Check for main PLL */ 373177ba1f9SLey Foon Tan if (main0periph1 == 0) { 374177ba1f9SLey Foon Tan /* 375177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 376177ba1f9SLey Foon Tan * not sourced from main PLL 377177ba1f9SLey Foon Tan */ 378177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 379177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) 380177ba1f9SLey Foon Tan return 0; 381177ba1f9SLey Foon Tan 382177ba1f9SLey Foon Tan /* 383177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock is sourced from main PLL 384177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 385177ba1f9SLey Foon Tan */ 386177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 387177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 388177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 389177ba1f9SLey Foon Tan return 1; 390177ba1f9SLey Foon Tan 391177ba1f9SLey Foon Tan /* 392177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock is sourced from main PLL 393177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 394177ba1f9SLey Foon Tan */ 395177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && 396177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 397177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 398177ba1f9SLey Foon Tan return 2; 399177ba1f9SLey Foon Tan 400177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 401177ba1f9SLey Foon Tan /* 402177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 403177ba1f9SLey Foon Tan * not sourced from periph PLL 404177ba1f9SLey Foon Tan */ 405177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 406177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) 407177ba1f9SLey Foon Tan return 0; 408177ba1f9SLey Foon Tan 409177ba1f9SLey Foon Tan /* 410177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock are source from periph PLL 411177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 412177ba1f9SLey Foon Tan */ 413177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 414177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 415177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 416177ba1f9SLey Foon Tan return 1; 417177ba1f9SLey Foon Tan 418177ba1f9SLey Foon Tan /* 419177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock are source from periph PLL 420177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 421177ba1f9SLey Foon Tan */ 422177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && 423177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 424177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 425177ba1f9SLey Foon Tan return 2; 426177ba1f9SLey Foon Tan } 427177ba1f9SLey Foon Tan 428177ba1f9SLey Foon Tan return 0; 429177ba1f9SLey Foon Tan } 430177ba1f9SLey Foon Tan 431177ba1f9SLey Foon Tan static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, 432177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 433177ba1f9SLey Foon Tan u32 safe_hz, u32 clk_hz) 434177ba1f9SLey Foon Tan { 435177ba1f9SLey Foon Tan u32 cnt; 436177ba1f9SLey Foon Tan u32 clk; 437177ba1f9SLey Foon Tan u32 shift; 438177ba1f9SLey Foon Tan u32 mask; 439177ba1f9SLey Foon Tan u32 denom; 440177ba1f9SLey Foon Tan 441177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 442177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 443177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 444177ba1f9SLey Foon Tan shift = 0; 445177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 446177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 447177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 448177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 449177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 450177ba1f9SLey Foon Tan shift = 0; 451177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 452177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 453177ba1f9SLey Foon Tan } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 454177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 455177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 456177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; 457177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 458177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 459177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 460177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 461177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 462177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; 463177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 464177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 465177ba1f9SLey Foon Tan } else { 466177ba1f9SLey Foon Tan return 0; 467177ba1f9SLey Foon Tan } 468177ba1f9SLey Foon Tan 469177ba1f9SLey Foon Tan return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * 470177ba1f9SLey Foon Tan (1 + denom) - 1; 471177ba1f9SLey Foon Tan } 472177ba1f9SLey Foon Tan 473177ba1f9SLey Foon Tan /* 474177ba1f9SLey Foon Tan * Calculate the new PLL numerator which is based on existing DTS hand off and 475177ba1f9SLey Foon Tan * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the 476177ba1f9SLey Foon Tan * numerator while maintaining denominator as denominator will influence the 477177ba1f9SLey Foon Tan * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final 478177ba1f9SLey Foon Tan * value for numerator is minus with 1 to cater our register value 479177ba1f9SLey Foon Tan * representation. 480177ba1f9SLey Foon Tan */ 481177ba1f9SLey Foon Tan static unsigned int cm_calc_safe_pll_numer(int main0periph1, 482177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 483177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 484177ba1f9SLey Foon Tan unsigned int safe_hz) 485177ba1f9SLey Foon Tan { 486177ba1f9SLey Foon Tan unsigned int clk_hz = 0; 487177ba1f9SLey Foon Tan 488177ba1f9SLey Foon Tan /* Check for main PLL */ 489177ba1f9SLey Foon Tan if (main0periph1 == 0) { 490177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 491177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 492177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 493177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 494177ba1f9SLey Foon Tan break; 495177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 496177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 497177ba1f9SLey Foon Tan break; 498177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 499177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 500177ba1f9SLey Foon Tan break; 501177ba1f9SLey Foon Tan default: 502177ba1f9SLey Foon Tan return 0; 503177ba1f9SLey Foon Tan } 504177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 505177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ 506177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 507177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 508177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 509177ba1f9SLey Foon Tan break; 510177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 511177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 512177ba1f9SLey Foon Tan break; 513177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 514177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 515177ba1f9SLey Foon Tan break; 516177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 517177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 518177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 519177ba1f9SLey Foon Tan break; 520177ba1f9SLey Foon Tan default: 521177ba1f9SLey Foon Tan return 0; 522177ba1f9SLey Foon Tan } 523177ba1f9SLey Foon Tan } else { 524177ba1f9SLey Foon Tan return 0; 525177ba1f9SLey Foon Tan } 526177ba1f9SLey Foon Tan 527177ba1f9SLey Foon Tan return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); 528177ba1f9SLey Foon Tan } 529177ba1f9SLey Foon Tan 530177ba1f9SLey Foon Tan /* ramping the main PLL to final value */ 531177ba1f9SLey Foon Tan static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, 532177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 533177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz) 534177ba1f9SLey Foon Tan { 535177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 536177ba1f9SLey Foon Tan 537177ba1f9SLey Foon Tan /* find out the increment value */ 538177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 539177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 540177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 541177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 542177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 543177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 544177ba1f9SLey Foon Tan } 545177ba1f9SLey Foon Tan 546177ba1f9SLey Foon Tan /* execute the ramping here */ 547177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_main_hz + clk_incr_hz; 548177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 549177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << 550177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 551177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), 552177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 553177ba1f9SLey Foon Tan mdelay(1); 554177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 555177ba1f9SLey Foon Tan } 556177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 557177ba1f9SLey Foon Tan main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); 558177ba1f9SLey Foon Tan mdelay(1); 559177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 560177ba1f9SLey Foon Tan } 561177ba1f9SLey Foon Tan 562177ba1f9SLey Foon Tan /* ramping the periph PLL to final value */ 563177ba1f9SLey Foon Tan static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, 564177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 565177ba1f9SLey Foon Tan unsigned int pll_ramp_periph_hz) 566177ba1f9SLey Foon Tan { 567177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 568177ba1f9SLey Foon Tan 569177ba1f9SLey Foon Tan /* find out the increment value */ 570177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 571177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 572177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 573177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 574177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 575177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 576177ba1f9SLey Foon Tan } 577177ba1f9SLey Foon Tan /* execute the ramping here */ 578177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; 579177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 580177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 581177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), 582177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 583177ba1f9SLey Foon Tan mdelay(1); 584177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 585177ba1f9SLey Foon Tan } 586177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 587177ba1f9SLey Foon Tan per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); 588177ba1f9SLey Foon Tan mdelay(1); 589177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 590177ba1f9SLey Foon Tan } 591177ba1f9SLey Foon Tan 592177ba1f9SLey Foon Tan /* 593177ba1f9SLey Foon Tan * Setup clocks while making no assumptions of the 594177ba1f9SLey Foon Tan * previous state of the clocks. 595177ba1f9SLey Foon Tan * 596177ba1f9SLey Foon Tan * Start by being paranoid and gate all sw managed clocks 597177ba1f9SLey Foon Tan * 598177ba1f9SLey Foon Tan * Put all plls in bypass 599177ba1f9SLey Foon Tan * 600177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value (bgpwr dwn). 601177ba1f9SLey Foon Tan * 602177ba1f9SLey Foon Tan * Put peripheral and main pll src to reset value to avoid glitch. 603177ba1f9SLey Foon Tan * 604177ba1f9SLey Foon Tan * Delay 5 us. 605177ba1f9SLey Foon Tan * 606177ba1f9SLey Foon Tan * Deassert bg pwr dn and set numerator and denominator 607177ba1f9SLey Foon Tan * 608177ba1f9SLey Foon Tan * Start 7 us timer. 609177ba1f9SLey Foon Tan * 610177ba1f9SLey Foon Tan * set internal dividers 611177ba1f9SLey Foon Tan * 612177ba1f9SLey Foon Tan * Wait for 7 us timer. 613177ba1f9SLey Foon Tan * 614177ba1f9SLey Foon Tan * Enable plls 615177ba1f9SLey Foon Tan * 616177ba1f9SLey Foon Tan * Set external dividers while plls are locking 617177ba1f9SLey Foon Tan * 618177ba1f9SLey Foon Tan * Wait for pll lock 619177ba1f9SLey Foon Tan * 620177ba1f9SLey Foon Tan * Assert/deassert outreset all. 621177ba1f9SLey Foon Tan * 622177ba1f9SLey Foon Tan * Take all pll's out of bypass 623177ba1f9SLey Foon Tan * 624177ba1f9SLey Foon Tan * Clear safe mode 625177ba1f9SLey Foon Tan * 626177ba1f9SLey Foon Tan * set source main and peripheral clocks 627177ba1f9SLey Foon Tan * 628177ba1f9SLey Foon Tan * Ungate clocks 629177ba1f9SLey Foon Tan */ 630177ba1f9SLey Foon Tan 631177ba1f9SLey Foon Tan static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 632177ba1f9SLey Foon Tan { 633177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, 634177ba1f9SLey Foon Tan ramp_required; 635177ba1f9SLey Foon Tan 636177ba1f9SLey Foon Tan /* gate off all mainpll clock excpet HW managed clock */ 637177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 638177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 639177ba1f9SLey Foon Tan &clock_manager_base->main_pll.enr); 640177ba1f9SLey Foon Tan 641177ba1f9SLey Foon Tan /* now we can gate off the rest of the peripheral clocks */ 642177ba1f9SLey Foon Tan writel(0, &clock_manager_base->per_pll.en); 643177ba1f9SLey Foon Tan 644177ba1f9SLey Foon Tan /* Put all plls in external bypass */ 645177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 646177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypasss); 647177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 648177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypasss); 649177ba1f9SLey Foon Tan 650177ba1f9SLey Foon Tan /* 651177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value. 652177ba1f9SLey Foon Tan * Some code might have messed with them. At same time set the 653177ba1f9SLey Foon Tan * desired clock source 654177ba1f9SLey Foon Tan */ 655177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO0_RESET | 656177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | 657177ba1f9SLey Foon Tan (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), 658177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 659177ba1f9SLey Foon Tan 660177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO0_RESET | 661177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | 662177ba1f9SLey Foon Tan (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), 663177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 664177ba1f9SLey Foon Tan 665177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); 666177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); 667177ba1f9SLey Foon Tan 668177ba1f9SLey Foon Tan /* clear the interrupt register status register */ 669177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 670177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 671177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 672177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 673177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 674177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | 675177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | 676177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, 677177ba1f9SLey Foon Tan &clock_manager_base->intr); 678177ba1f9SLey Foon Tan 679177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for main PLL */ 680177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); 681177ba1f9SLey Foon Tan if (ramp_required) { 682177ba1f9SLey Foon Tan /* set main PLL to safe starting threshold frequency */ 683177ba1f9SLey Foon Tan if (ramp_required == 1) 684177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 685177ba1f9SLey Foon Tan else if (ramp_required == 2) 686177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 687177ba1f9SLey Foon Tan 688177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 689177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, 690177ba1f9SLey Foon Tan pll_ramp_main_hz), 691177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 692177ba1f9SLey Foon Tan } else 693177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 694177ba1f9SLey Foon Tan main_cfg->vco1_numer, 695177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 696177ba1f9SLey Foon Tan 697177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for periph PLL */ 698177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); 699177ba1f9SLey Foon Tan if (ramp_required) { 700177ba1f9SLey Foon Tan /* set periph PLL to safe starting threshold frequency */ 701177ba1f9SLey Foon Tan if (ramp_required == 1) 702177ba1f9SLey Foon Tan pll_ramp_periph_hz = 703177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 704177ba1f9SLey Foon Tan else if (ramp_required == 2) 705177ba1f9SLey Foon Tan pll_ramp_periph_hz = 706177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 707177ba1f9SLey Foon Tan 708177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 709177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, 710177ba1f9SLey Foon Tan pll_ramp_periph_hz), 711177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 712177ba1f9SLey Foon Tan } else 713177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 714177ba1f9SLey Foon Tan per_cfg->vco1_numer, 715177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 716177ba1f9SLey Foon Tan 717177ba1f9SLey Foon Tan /* Wait for at least 5 us */ 718177ba1f9SLey Foon Tan udelay(5); 719177ba1f9SLey Foon Tan 720177ba1f9SLey Foon Tan /* Now deassert BGPWRDN and PWRDN */ 721177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 722177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | 723177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); 724177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 725177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | 726177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); 727177ba1f9SLey Foon Tan 728177ba1f9SLey Foon Tan /* Wait for at least 7 us */ 729177ba1f9SLey Foon Tan udelay(7); 730177ba1f9SLey Foon Tan 731177ba1f9SLey Foon Tan /* enable the VCO and disable the external regulator to PLL */ 732177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->main_pll.vco0) & 733177ba1f9SLey Foon Tan ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | 734177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_EN_SET_MSK, 735177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 736177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->per_pll.vco0) & 737177ba1f9SLey Foon Tan ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | 738177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_EN_SET_MSK, 739177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 740177ba1f9SLey Foon Tan 741177ba1f9SLey Foon Tan /* setup all the main PLL counter and clock source */ 742177ba1f9SLey Foon Tan writel(main_cfg->nocclk, 743177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); 744177ba1f9SLey Foon Tan writel(main_cfg->mpuclk, 745177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); 746177ba1f9SLey Foon Tan 747177ba1f9SLey Foon Tan /* main_emaca_clk divider */ 748177ba1f9SLey Foon Tan writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); 749177ba1f9SLey Foon Tan /* main_emacb_clk divider */ 750177ba1f9SLey Foon Tan writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); 751177ba1f9SLey Foon Tan /* main_emac_ptp_clk divider */ 752177ba1f9SLey Foon Tan writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); 753177ba1f9SLey Foon Tan /* main_gpio_db_clk divider */ 754177ba1f9SLey Foon Tan writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); 755177ba1f9SLey Foon Tan /* main_sdmmc_clk divider */ 756177ba1f9SLey Foon Tan writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); 757177ba1f9SLey Foon Tan /* main_s2f_user0_clk divider */ 758177ba1f9SLey Foon Tan writel(main_cfg->cntr7clk_cnt | 759177ba1f9SLey Foon Tan (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), 760177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr7clk); 761177ba1f9SLey Foon Tan /* main_s2f_user1_clk divider */ 762177ba1f9SLey Foon Tan writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); 763177ba1f9SLey Foon Tan /* main_hmc_pll_clk divider */ 764177ba1f9SLey Foon Tan writel(main_cfg->cntr9clk_cnt | 765177ba1f9SLey Foon Tan (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), 766177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr9clk); 767177ba1f9SLey Foon Tan /* main_periph_ref_clk divider */ 768177ba1f9SLey Foon Tan writel(main_cfg->cntr15clk_cnt, 769177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr15clk); 770177ba1f9SLey Foon Tan 771177ba1f9SLey Foon Tan /* setup all the peripheral PLL counter and clock source */ 772177ba1f9SLey Foon Tan /* peri_emaca_clk divider */ 773177ba1f9SLey Foon Tan writel(per_cfg->cntr2clk_cnt | 774177ba1f9SLey Foon Tan (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), 775177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr2clk); 776177ba1f9SLey Foon Tan /* peri_emacb_clk divider */ 777177ba1f9SLey Foon Tan writel(per_cfg->cntr3clk_cnt | 778177ba1f9SLey Foon Tan (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), 779177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr3clk); 780177ba1f9SLey Foon Tan /* peri_emac_ptp_clk divider */ 781177ba1f9SLey Foon Tan writel(per_cfg->cntr4clk_cnt | 782177ba1f9SLey Foon Tan (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), 783177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr4clk); 784177ba1f9SLey Foon Tan /* peri_gpio_db_clk divider */ 785177ba1f9SLey Foon Tan writel(per_cfg->cntr5clk_cnt | 786177ba1f9SLey Foon Tan (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), 787177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr5clk); 788177ba1f9SLey Foon Tan /* peri_sdmmc_clk divider */ 789177ba1f9SLey Foon Tan writel(per_cfg->cntr6clk_cnt | 790177ba1f9SLey Foon Tan (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), 791177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr6clk); 792177ba1f9SLey Foon Tan /* peri_s2f_user0_clk divider */ 793177ba1f9SLey Foon Tan writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); 794177ba1f9SLey Foon Tan /* peri_s2f_user1_clk divider */ 795177ba1f9SLey Foon Tan writel(per_cfg->cntr8clk_cnt | 796177ba1f9SLey Foon Tan (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), 797177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr8clk); 798177ba1f9SLey Foon Tan /* peri_hmc_pll_clk divider */ 799177ba1f9SLey Foon Tan writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); 800177ba1f9SLey Foon Tan 801177ba1f9SLey Foon Tan /* setup all the external PLL counter */ 802177ba1f9SLey Foon Tan /* mpu wrapper / external divider */ 803177ba1f9SLey Foon Tan writel(main_cfg->mpuclk_cnt | 804177ba1f9SLey Foon Tan (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), 805177ba1f9SLey Foon Tan &clock_manager_base->main_pll.mpuclk); 806177ba1f9SLey Foon Tan /* NOC wrapper / external divider */ 807177ba1f9SLey Foon Tan writel(main_cfg->nocclk_cnt | 808177ba1f9SLey Foon Tan (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), 809177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocclk); 810177ba1f9SLey Foon Tan /* NOC subclock divider such as l4 */ 811177ba1f9SLey Foon Tan writel(main_cfg->nocdiv_l4mainclk | 812177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4mpclk << 813177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | 814177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4spclk << 815177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | 816177ba1f9SLey Foon Tan (main_cfg->nocdiv_csatclk << 817177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | 818177ba1f9SLey Foon Tan (main_cfg->nocdiv_cstraceclk << 819177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | 820177ba1f9SLey Foon Tan (main_cfg->nocdiv_cspdbclk << 821177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), 822177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocdiv); 823177ba1f9SLey Foon Tan /* gpio_db external divider */ 824177ba1f9SLey Foon Tan writel(per_cfg->gpiodiv_gpiodbclk, 825177ba1f9SLey Foon Tan &clock_manager_base->per_pll.gpiodiv); 826177ba1f9SLey Foon Tan 827177ba1f9SLey Foon Tan /* setup the EMAC clock mux select */ 828177ba1f9SLey Foon Tan writel((per_cfg->emacctl_emac0sel << 829177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | 830177ba1f9SLey Foon Tan (per_cfg->emacctl_emac1sel << 831177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | 832177ba1f9SLey Foon Tan (per_cfg->emacctl_emac2sel << 833177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), 834177ba1f9SLey Foon Tan &clock_manager_base->per_pll.emacctl); 835177ba1f9SLey Foon Tan 836177ba1f9SLey Foon Tan /* at this stage, check for PLL lock status */ 837177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 838177ba1f9SLey Foon Tan 839177ba1f9SLey Foon Tan /* 840177ba1f9SLey Foon Tan * after locking, but before taking out of bypass, 841177ba1f9SLey Foon Tan * assert/deassert outresetall 842177ba1f9SLey Foon Tan */ 843177ba1f9SLey Foon Tan /* assert mainpll outresetall */ 844177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->main_pll.vco0, 845177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 846177ba1f9SLey Foon Tan /* assert perpll outresetall */ 847177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->per_pll.vco0, 848177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 849177ba1f9SLey Foon Tan /* de-assert mainpll outresetall */ 850177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 851177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 852177ba1f9SLey Foon Tan /* de-assert perpll outresetall */ 853177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 854177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 855177ba1f9SLey Foon Tan 856177ba1f9SLey Foon Tan /* Take all PLLs out of bypass when boot mode is cleared. */ 857177ba1f9SLey Foon Tan /* release mainpll from bypass */ 858177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 859177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypassr); 860177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 861177ba1f9SLey Foon Tan cm_wait_for_fsm(); 862177ba1f9SLey Foon Tan 863177ba1f9SLey Foon Tan /* release perpll from bypass */ 864177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 865177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypassr); 866177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 867177ba1f9SLey Foon Tan cm_wait_for_fsm(); 868177ba1f9SLey Foon Tan 869177ba1f9SLey Foon Tan /* clear boot mode */ 870177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->ctrl, 871177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); 872177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 873177ba1f9SLey Foon Tan cm_wait_for_fsm(); 874177ba1f9SLey Foon Tan 875177ba1f9SLey Foon Tan /* At here, we need to ramp to final value if needed */ 876177ba1f9SLey Foon Tan if (pll_ramp_main_hz != 0) 877177ba1f9SLey Foon Tan cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); 878177ba1f9SLey Foon Tan if (pll_ramp_periph_hz != 0) 879177ba1f9SLey Foon Tan cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); 880177ba1f9SLey Foon Tan 881177ba1f9SLey Foon Tan /* Now ungate non-hw-managed clocks */ 882177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 883177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 884177ba1f9SLey Foon Tan &clock_manager_base->main_pll.ens); 885177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); 886177ba1f9SLey Foon Tan 887177ba1f9SLey Foon Tan /* Clear the loss lock and slip bits as they might set during 888177ba1f9SLey Foon Tan clock reconfiguration */ 889177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 890177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 891177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 892177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 893177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 894177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, 895177ba1f9SLey Foon Tan &clock_manager_base->intr); 896177ba1f9SLey Foon Tan 897177ba1f9SLey Foon Tan return 0; 898177ba1f9SLey Foon Tan } 899177ba1f9SLey Foon Tan 900177ba1f9SLey Foon Tan void cm_use_intosc(void) 901177ba1f9SLey Foon Tan { 902177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->ctrl, 903177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); 904177ba1f9SLey Foon Tan } 905177ba1f9SLey Foon Tan 906177ba1f9SLey Foon Tan int cm_basic_init(const void *blob) 907177ba1f9SLey Foon Tan { 908177ba1f9SLey Foon Tan struct mainpll_cfg main_cfg; 909177ba1f9SLey Foon Tan struct perpll_cfg per_cfg; 910177ba1f9SLey Foon Tan int rval; 911177ba1f9SLey Foon Tan 912177ba1f9SLey Foon Tan /* initialize to zero for use case of optional node */ 913177ba1f9SLey Foon Tan memset(&main_cfg, 0, sizeof(main_cfg)); 914177ba1f9SLey Foon Tan memset(&per_cfg, 0, sizeof(per_cfg)); 915177ba1f9SLey Foon Tan 916480f7f9cSMarek Vasut rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); 917177ba1f9SLey Foon Tan if (rval) 918177ba1f9SLey Foon Tan return rval; 919177ba1f9SLey Foon Tan 920f4c3e0dcSMarek Vasut return cm_full_cfg(&main_cfg, &per_cfg); 921177ba1f9SLey Foon Tan } 922177ba1f9SLey Foon Tan 923*d81b5da3SMarek Vasut static u32 cm_get_rate_dm(char *name) 924*d81b5da3SMarek Vasut { 925*d81b5da3SMarek Vasut struct uclass *uc; 926*d81b5da3SMarek Vasut struct udevice *dev = NULL; 927*d81b5da3SMarek Vasut struct clk clk = { 0 }; 928*d81b5da3SMarek Vasut ulong rate; 929*d81b5da3SMarek Vasut int ret; 930*d81b5da3SMarek Vasut 931*d81b5da3SMarek Vasut /* Device addresses start at 1 */ 932*d81b5da3SMarek Vasut ret = uclass_get(UCLASS_CLK, &uc); 933*d81b5da3SMarek Vasut if (ret) 934*d81b5da3SMarek Vasut return 0; 935*d81b5da3SMarek Vasut 936*d81b5da3SMarek Vasut ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev); 937*d81b5da3SMarek Vasut if (ret) 938*d81b5da3SMarek Vasut return 0; 939*d81b5da3SMarek Vasut 940*d81b5da3SMarek Vasut ret = device_probe(dev); 941*d81b5da3SMarek Vasut if (ret) 942*d81b5da3SMarek Vasut return 0; 943*d81b5da3SMarek Vasut 944*d81b5da3SMarek Vasut ret = clk_request(dev, &clk); 945*d81b5da3SMarek Vasut if (ret) 946*d81b5da3SMarek Vasut return 0; 947*d81b5da3SMarek Vasut 948*d81b5da3SMarek Vasut rate = clk_get_rate(&clk); 949*d81b5da3SMarek Vasut 950*d81b5da3SMarek Vasut clk_free(&clk); 951*d81b5da3SMarek Vasut 952*d81b5da3SMarek Vasut return rate; 953*d81b5da3SMarek Vasut } 954*d81b5da3SMarek Vasut 955*d81b5da3SMarek Vasut static u32 cm_get_rate_dm_khz(char *name) 956*d81b5da3SMarek Vasut { 957*d81b5da3SMarek Vasut return cm_get_rate_dm(name) / 1000; 958*d81b5da3SMarek Vasut } 959*d81b5da3SMarek Vasut 960177ba1f9SLey Foon Tan unsigned long cm_get_mpu_clk_hz(void) 961177ba1f9SLey Foon Tan { 962*d81b5da3SMarek Vasut return cm_get_rate_dm("main_mpu_base_clk"); 963177ba1f9SLey Foon Tan } 964177ba1f9SLey Foon Tan 965177ba1f9SLey Foon Tan unsigned int cm_get_qspi_controller_clk_hz(void) 966177ba1f9SLey Foon Tan { 967*d81b5da3SMarek Vasut return cm_get_rate_dm("qspi_clk"); 968177ba1f9SLey Foon Tan } 969177ba1f9SLey Foon Tan 970*d81b5da3SMarek Vasut unsigned int cm_get_l4_sp_clk_hz(void) 97121143ce1SEugeniy Paltsev { 972*d81b5da3SMarek Vasut return cm_get_rate_dm("l4_sp_clk"); 97321143ce1SEugeniy Paltsev } 97421143ce1SEugeniy Paltsev 975177ba1f9SLey Foon Tan void cm_print_clock_quick_summary(void) 976177ba1f9SLey Foon Tan { 977*d81b5da3SMarek Vasut printf("MPU %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk")); 978*d81b5da3SMarek Vasut printf("MMC %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk")); 979*d81b5da3SMarek Vasut printf("QSPI %8d kHz\n", cm_get_rate_dm_khz("qspi_clk")); 980*d81b5da3SMarek Vasut printf("SPI %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk")); 981*d81b5da3SMarek Vasut printf("EOSC1 %8d kHz\n", cm_get_rate_dm_khz("osc1")); 982*d81b5da3SMarek Vasut printf("cb_intosc %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk")); 983*d81b5da3SMarek Vasut printf("f2s_free %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk")); 984*d81b5da3SMarek Vasut printf("Main VCO %8d kHz\n", cm_get_rate_dm_khz("main_pll@40")); 985*d81b5da3SMarek Vasut printf("NOC %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk")); 986*d81b5da3SMarek Vasut printf("L4 Main %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk")); 987*d81b5da3SMarek Vasut printf("L4 MP %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk")); 988*d81b5da3SMarek Vasut printf("L4 SP %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk")); 989*d81b5da3SMarek Vasut printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk")); 990177ba1f9SLey Foon Tan } 991