183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2177ba1f9SLey Foon Tan /* 3177ba1f9SLey Foon Tan * Copyright (C) 2016-2017 Intel Corporation 4177ba1f9SLey Foon Tan */ 5177ba1f9SLey Foon Tan 6177ba1f9SLey Foon Tan #include <common.h> 7177ba1f9SLey Foon Tan #include <fdtdec.h> 8177ba1f9SLey Foon Tan #include <asm/io.h> 921143ce1SEugeniy Paltsev #include <dm.h> 10*934aec71SMarek Vasut #include <clk.h> 11*934aec71SMarek Vasut #include <dm/device-internal.h> 12177ba1f9SLey Foon Tan #include <asm/arch/clock_manager.h> 13177ba1f9SLey Foon Tan 14480f7f9cSMarek Vasut static const struct socfpga_clock_manager *clock_manager_base = 15480f7f9cSMarek Vasut (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 16480f7f9cSMarek Vasut 17177ba1f9SLey Foon Tan static u32 eosc1_hz; 18177ba1f9SLey Foon Tan static u32 cb_intosc_hz; 19177ba1f9SLey Foon Tan static u32 f2s_free_hz; 20177ba1f9SLey Foon Tan static u32 cm_l4_main_clk_hz; 21177ba1f9SLey Foon Tan static u32 cm_l4_sp_clk_hz; 22177ba1f9SLey Foon Tan static u32 cm_l4_mp_clk_hz; 23177ba1f9SLey Foon Tan static u32 cm_l4_sys_free_clk_hz; 24177ba1f9SLey Foon Tan 25177ba1f9SLey Foon Tan struct mainpll_cfg { 26177ba1f9SLey Foon Tan u32 vco0_psrc; 27177ba1f9SLey Foon Tan u32 vco1_denom; 28177ba1f9SLey Foon Tan u32 vco1_numer; 29177ba1f9SLey Foon Tan u32 mpuclk; 30177ba1f9SLey Foon Tan u32 mpuclk_cnt; 31177ba1f9SLey Foon Tan u32 mpuclk_src; 32177ba1f9SLey Foon Tan u32 nocclk; 33177ba1f9SLey Foon Tan u32 nocclk_cnt; 34177ba1f9SLey Foon Tan u32 nocclk_src; 35177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 36177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 37177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 38177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 39177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 40177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 41177ba1f9SLey Foon Tan u32 cntr7clk_src; 42177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 43177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 44177ba1f9SLey Foon Tan u32 cntr9clk_src; 45177ba1f9SLey Foon Tan u32 cntr15clk_cnt; 46177ba1f9SLey Foon Tan u32 nocdiv_l4mainclk; 47177ba1f9SLey Foon Tan u32 nocdiv_l4mpclk; 48177ba1f9SLey Foon Tan u32 nocdiv_l4spclk; 49177ba1f9SLey Foon Tan u32 nocdiv_csatclk; 50177ba1f9SLey Foon Tan u32 nocdiv_cstraceclk; 51177ba1f9SLey Foon Tan u32 nocdiv_cspdbclk; 52177ba1f9SLey Foon Tan }; 53177ba1f9SLey Foon Tan 54177ba1f9SLey Foon Tan struct perpll_cfg { 55177ba1f9SLey Foon Tan u32 vco0_psrc; 56177ba1f9SLey Foon Tan u32 vco1_denom; 57177ba1f9SLey Foon Tan u32 vco1_numer; 58177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 59177ba1f9SLey Foon Tan u32 cntr2clk_src; 60177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 61177ba1f9SLey Foon Tan u32 cntr3clk_src; 62177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 63177ba1f9SLey Foon Tan u32 cntr4clk_src; 64177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 65177ba1f9SLey Foon Tan u32 cntr5clk_src; 66177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 67177ba1f9SLey Foon Tan u32 cntr6clk_src; 68177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 69177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 70177ba1f9SLey Foon Tan u32 cntr8clk_src; 71177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 72480f7f9cSMarek Vasut u32 cntr9clk_src; 73177ba1f9SLey Foon Tan u32 emacctl_emac0sel; 74177ba1f9SLey Foon Tan u32 emacctl_emac1sel; 75177ba1f9SLey Foon Tan u32 emacctl_emac2sel; 76177ba1f9SLey Foon Tan u32 gpiodiv_gpiodbclk; 77177ba1f9SLey Foon Tan }; 78177ba1f9SLey Foon Tan 79480f7f9cSMarek Vasut struct strtou32 { 80480f7f9cSMarek Vasut const char *str; 81480f7f9cSMarek Vasut const u32 val; 82177ba1f9SLey Foon Tan }; 83177ba1f9SLey Foon Tan 84480f7f9cSMarek Vasut static const struct strtou32 mainpll_cfg_tab[] = { 85480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, 86480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, 87480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, 88480f7f9cSMarek Vasut { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, 89480f7f9cSMarek Vasut { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, 90480f7f9cSMarek Vasut { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, 91480f7f9cSMarek Vasut { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) }, 92480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) }, 93480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) }, 94480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) }, 95480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) }, 96480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) }, 97480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) }, 98480f7f9cSMarek Vasut { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) }, 99480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) }, 100480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) }, 101480f7f9cSMarek Vasut { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) }, 102480f7f9cSMarek Vasut { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) }, 103480f7f9cSMarek Vasut { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) }, 104480f7f9cSMarek Vasut { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) }, 105480f7f9cSMarek Vasut { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) }, 106480f7f9cSMarek Vasut { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) }, 107480f7f9cSMarek Vasut { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) }, 108480f7f9cSMarek Vasut { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) }, 109480f7f9cSMarek Vasut }; 110177ba1f9SLey Foon Tan 111480f7f9cSMarek Vasut static const struct strtou32 perpll_cfg_tab[] = { 112480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) }, 113480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) }, 114480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) }, 115480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) }, 116480f7f9cSMarek Vasut { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) }, 117480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) }, 118480f7f9cSMarek Vasut { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) }, 119480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) }, 120480f7f9cSMarek Vasut { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) }, 121480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) }, 122480f7f9cSMarek Vasut { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) }, 123480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) }, 124480f7f9cSMarek Vasut { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) }, 125480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) }, 126480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) }, 127480f7f9cSMarek Vasut { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) }, 128480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) }, 129480f7f9cSMarek Vasut { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) }, 130480f7f9cSMarek Vasut { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) }, 131480f7f9cSMarek Vasut { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) }, 132480f7f9cSMarek Vasut { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) }, 133480f7f9cSMarek Vasut }; 134480f7f9cSMarek Vasut 135480f7f9cSMarek Vasut static const struct strtou32 alteragrp_cfg_tab[] = { 136480f7f9cSMarek Vasut { "nocclk", offsetof(struct mainpll_cfg, nocclk) }, 137480f7f9cSMarek Vasut { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) }, 138480f7f9cSMarek Vasut }; 139480f7f9cSMarek Vasut 140480f7f9cSMarek Vasut struct strtopu32 { 141480f7f9cSMarek Vasut const char *str; 142480f7f9cSMarek Vasut u32 *p; 143480f7f9cSMarek Vasut }; 144480f7f9cSMarek Vasut 145480f7f9cSMarek Vasut const struct strtopu32 dt_to_val[] = { 146*934aec71SMarek Vasut { "altera_arria10_hps_eosc1", &eosc1_hz }, 147*934aec71SMarek Vasut { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, 148*934aec71SMarek Vasut { "altera_arria10_hps_f2h_free", &f2s_free_hz }, 149480f7f9cSMarek Vasut }; 150480f7f9cSMarek Vasut 151480f7f9cSMarek Vasut static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, 152480f7f9cSMarek Vasut int cfg_tab_len, void *cfg) 153177ba1f9SLey Foon Tan { 154480f7f9cSMarek Vasut int i; 155480f7f9cSMarek Vasut u32 val; 156480f7f9cSMarek Vasut 157480f7f9cSMarek Vasut for (i = 0; i < cfg_tab_len; i++) { 158480f7f9cSMarek Vasut if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) { 159177ba1f9SLey Foon Tan /* could not find required property */ 160177ba1f9SLey Foon Tan return -EINVAL; 161177ba1f9SLey Foon Tan } 162480f7f9cSMarek Vasut *(u32 *)(cfg + cfg_tab[i].val) = val; 163480f7f9cSMarek Vasut } 164177ba1f9SLey Foon Tan 165177ba1f9SLey Foon Tan return 0; 166177ba1f9SLey Foon Tan } 167177ba1f9SLey Foon Tan 168*934aec71SMarek Vasut static int of_get_input_clks(const void *blob) 169177ba1f9SLey Foon Tan { 170*934aec71SMarek Vasut struct udevice *dev; 171*934aec71SMarek Vasut struct clk clk; 172*934aec71SMarek Vasut int i, ret; 173177ba1f9SLey Foon Tan 174480f7f9cSMarek Vasut for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { 175*934aec71SMarek Vasut memset(&clk, 0, sizeof(clk)); 176480f7f9cSMarek Vasut 177*934aec71SMarek Vasut ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, 178*934aec71SMarek Vasut &dev); 179*934aec71SMarek Vasut if (ret) 180*934aec71SMarek Vasut return ret; 181480f7f9cSMarek Vasut 182*934aec71SMarek Vasut ret = clk_request(dev, &clk); 183*934aec71SMarek Vasut if (ret) 184*934aec71SMarek Vasut return ret; 185*934aec71SMarek Vasut 186*934aec71SMarek Vasut *dt_to_val[i].p = clk_get_rate(&clk); 187480f7f9cSMarek Vasut } 188*934aec71SMarek Vasut 189*934aec71SMarek Vasut return 0; 190177ba1f9SLey Foon Tan } 191177ba1f9SLey Foon Tan 192177ba1f9SLey Foon Tan static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, 193480f7f9cSMarek Vasut struct perpll_cfg *per_cfg) 194177ba1f9SLey Foon Tan { 195*934aec71SMarek Vasut int ret, node, child, len; 196177ba1f9SLey Foon Tan const char *node_name; 197177ba1f9SLey Foon Tan 198*934aec71SMarek Vasut ret = of_get_input_clks(blob); 199*934aec71SMarek Vasut if (ret) 200*934aec71SMarek Vasut return ret; 201480f7f9cSMarek Vasut 202480f7f9cSMarek Vasut node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); 203480f7f9cSMarek Vasut 204177ba1f9SLey Foon Tan if (node < 0) 205177ba1f9SLey Foon Tan return -EINVAL; 206177ba1f9SLey Foon Tan 207177ba1f9SLey Foon Tan child = fdt_first_subnode(blob, node); 208177ba1f9SLey Foon Tan 209177ba1f9SLey Foon Tan if (child < 0) 210177ba1f9SLey Foon Tan return -EINVAL; 211177ba1f9SLey Foon Tan 212177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 213177ba1f9SLey Foon Tan 214177ba1f9SLey Foon Tan while (node_name) { 215480f7f9cSMarek Vasut if (!strcmp(node_name, "mainpll")) { 216480f7f9cSMarek Vasut if (of_to_struct(blob, child, mainpll_cfg_tab, 217480f7f9cSMarek Vasut ARRAY_SIZE(mainpll_cfg_tab), main_cfg)) 218177ba1f9SLey Foon Tan return -EINVAL; 219480f7f9cSMarek Vasut } else if (!strcmp(node_name, "perpll")) { 220480f7f9cSMarek Vasut if (of_to_struct(blob, child, perpll_cfg_tab, 221480f7f9cSMarek Vasut ARRAY_SIZE(perpll_cfg_tab), per_cfg)) 222177ba1f9SLey Foon Tan return -EINVAL; 223480f7f9cSMarek Vasut } else if (!strcmp(node_name, "alteragrp")) { 224480f7f9cSMarek Vasut if (of_to_struct(blob, child, alteragrp_cfg_tab, 225480f7f9cSMarek Vasut ARRAY_SIZE(alteragrp_cfg_tab), main_cfg)) 226177ba1f9SLey Foon Tan return -EINVAL; 227177ba1f9SLey Foon Tan } 228177ba1f9SLey Foon Tan child = fdt_next_subnode(blob, child); 229177ba1f9SLey Foon Tan 230177ba1f9SLey Foon Tan if (child < 0) 231177ba1f9SLey Foon Tan break; 232177ba1f9SLey Foon Tan 233177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 234177ba1f9SLey Foon Tan } 235177ba1f9SLey Foon Tan 236177ba1f9SLey Foon Tan return 0; 237177ba1f9SLey Foon Tan } 238177ba1f9SLey Foon Tan 239177ba1f9SLey Foon Tan /* calculate the intended main VCO frequency based on handoff */ 240177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_main_vco_clk_hz 241177ba1f9SLey Foon Tan (struct mainpll_cfg *main_cfg) 242177ba1f9SLey Foon Tan { 243177ba1f9SLey Foon Tan unsigned int clk_hz; 244177ba1f9SLey Foon Tan 245177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 246177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 247177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 248177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 249177ba1f9SLey Foon Tan break; 250177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 251177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 252177ba1f9SLey Foon Tan break; 253177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 254177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 255177ba1f9SLey Foon Tan break; 256177ba1f9SLey Foon Tan default: 257177ba1f9SLey Foon Tan return 0; 258177ba1f9SLey Foon Tan } 259177ba1f9SLey Foon Tan 260177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 261177ba1f9SLey Foon Tan clk_hz /= 1 + main_cfg->vco1_denom; 262177ba1f9SLey Foon Tan clk_hz *= 1 + main_cfg->vco1_numer; 263177ba1f9SLey Foon Tan 264177ba1f9SLey Foon Tan return clk_hz; 265177ba1f9SLey Foon Tan } 266177ba1f9SLey Foon Tan 267177ba1f9SLey Foon Tan /* calculate the intended periph VCO frequency based on handoff */ 268177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_periph_vco_clk_hz( 269177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 270177ba1f9SLey Foon Tan { 271177ba1f9SLey Foon Tan unsigned int clk_hz; 272177ba1f9SLey Foon Tan 273177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ 274177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 275177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 276177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 277177ba1f9SLey Foon Tan break; 278177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 279177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 280177ba1f9SLey Foon Tan break; 281177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 282177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 283177ba1f9SLey Foon Tan break; 284177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 285177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 286177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 287177ba1f9SLey Foon Tan break; 288177ba1f9SLey Foon Tan default: 289177ba1f9SLey Foon Tan return 0; 290177ba1f9SLey Foon Tan } 291177ba1f9SLey Foon Tan 292177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 293177ba1f9SLey Foon Tan clk_hz /= 1 + per_cfg->vco1_denom; 294177ba1f9SLey Foon Tan clk_hz *= 1 + per_cfg->vco1_numer; 295177ba1f9SLey Foon Tan 296177ba1f9SLey Foon Tan return clk_hz; 297177ba1f9SLey Foon Tan } 298177ba1f9SLey Foon Tan 299177ba1f9SLey Foon Tan /* calculate the intended MPU clock frequency based on handoff */ 300177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, 301177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 302177ba1f9SLey Foon Tan { 303177ba1f9SLey Foon Tan unsigned int clk_hz; 304177ba1f9SLey Foon Tan 305177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 306177ba1f9SLey Foon Tan switch (main_cfg->mpuclk_src) { 307177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 308177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 309177ba1f9SLey Foon Tan clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) 310177ba1f9SLey Foon Tan + 1; 311177ba1f9SLey Foon Tan break; 312177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 313177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 314177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->mpuclk >> 315177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 316177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 317177ba1f9SLey Foon Tan break; 318177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 319177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 320177ba1f9SLey Foon Tan break; 321177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 322177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 323177ba1f9SLey Foon Tan break; 324177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 325177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 326177ba1f9SLey Foon Tan break; 327177ba1f9SLey Foon Tan default: 328177ba1f9SLey Foon Tan return 0; 329177ba1f9SLey Foon Tan } 330177ba1f9SLey Foon Tan 331177ba1f9SLey Foon Tan clk_hz /= main_cfg->mpuclk_cnt + 1; 332177ba1f9SLey Foon Tan return clk_hz; 333177ba1f9SLey Foon Tan } 334177ba1f9SLey Foon Tan 335177ba1f9SLey Foon Tan /* calculate the intended NOC clock frequency based on handoff */ 336177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, 337177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 338177ba1f9SLey Foon Tan { 339177ba1f9SLey Foon Tan unsigned int clk_hz; 340177ba1f9SLey Foon Tan 341177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 342177ba1f9SLey Foon Tan switch (main_cfg->nocclk_src) { 343177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: 344177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 345177ba1f9SLey Foon Tan clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) 346177ba1f9SLey Foon Tan + 1; 347177ba1f9SLey Foon Tan break; 348177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: 349177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 350177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->nocclk >> 351177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 352177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; 353177ba1f9SLey Foon Tan break; 354177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: 355177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 356177ba1f9SLey Foon Tan break; 357177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: 358177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 359177ba1f9SLey Foon Tan break; 360177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: 361177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 362177ba1f9SLey Foon Tan break; 363177ba1f9SLey Foon Tan default: 364177ba1f9SLey Foon Tan return 0; 365177ba1f9SLey Foon Tan } 366177ba1f9SLey Foon Tan 367177ba1f9SLey Foon Tan clk_hz /= main_cfg->nocclk_cnt + 1; 368177ba1f9SLey Foon Tan return clk_hz; 369177ba1f9SLey Foon Tan } 370177ba1f9SLey Foon Tan 371177ba1f9SLey Foon Tan /* return 1 if PLL ramp is required */ 372177ba1f9SLey Foon Tan static int cm_is_pll_ramp_required(int main0periph1, 373177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 374177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 375177ba1f9SLey Foon Tan { 376177ba1f9SLey Foon Tan /* Check for main PLL */ 377177ba1f9SLey Foon Tan if (main0periph1 == 0) { 378177ba1f9SLey Foon Tan /* 379177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 380177ba1f9SLey Foon Tan * not sourced from main PLL 381177ba1f9SLey Foon Tan */ 382177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 383177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) 384177ba1f9SLey Foon Tan return 0; 385177ba1f9SLey Foon Tan 386177ba1f9SLey Foon Tan /* 387177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock is sourced from main PLL 388177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 389177ba1f9SLey Foon Tan */ 390177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 391177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 392177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 393177ba1f9SLey Foon Tan return 1; 394177ba1f9SLey Foon Tan 395177ba1f9SLey Foon Tan /* 396177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock is sourced from main PLL 397177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 398177ba1f9SLey Foon Tan */ 399177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && 400177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 401177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 402177ba1f9SLey Foon Tan return 2; 403177ba1f9SLey Foon Tan 404177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 405177ba1f9SLey Foon Tan /* 406177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 407177ba1f9SLey Foon Tan * not sourced from periph PLL 408177ba1f9SLey Foon Tan */ 409177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 410177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) 411177ba1f9SLey Foon Tan return 0; 412177ba1f9SLey Foon Tan 413177ba1f9SLey Foon Tan /* 414177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock are source from periph PLL 415177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 416177ba1f9SLey Foon Tan */ 417177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 418177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 419177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 420177ba1f9SLey Foon Tan return 1; 421177ba1f9SLey Foon Tan 422177ba1f9SLey Foon Tan /* 423177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock are source from periph PLL 424177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 425177ba1f9SLey Foon Tan */ 426177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && 427177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 428177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 429177ba1f9SLey Foon Tan return 2; 430177ba1f9SLey Foon Tan } 431177ba1f9SLey Foon Tan 432177ba1f9SLey Foon Tan return 0; 433177ba1f9SLey Foon Tan } 434177ba1f9SLey Foon Tan 435177ba1f9SLey Foon Tan static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, 436177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 437177ba1f9SLey Foon Tan u32 safe_hz, u32 clk_hz) 438177ba1f9SLey Foon Tan { 439177ba1f9SLey Foon Tan u32 cnt; 440177ba1f9SLey Foon Tan u32 clk; 441177ba1f9SLey Foon Tan u32 shift; 442177ba1f9SLey Foon Tan u32 mask; 443177ba1f9SLey Foon Tan u32 denom; 444177ba1f9SLey Foon Tan 445177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 446177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 447177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 448177ba1f9SLey Foon Tan shift = 0; 449177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 450177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 451177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 452177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 453177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 454177ba1f9SLey Foon Tan shift = 0; 455177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 456177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 457177ba1f9SLey Foon Tan } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 458177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 459177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 460177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; 461177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 462177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 463177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 464177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 465177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 466177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; 467177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 468177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 469177ba1f9SLey Foon Tan } else { 470177ba1f9SLey Foon Tan return 0; 471177ba1f9SLey Foon Tan } 472177ba1f9SLey Foon Tan 473177ba1f9SLey Foon Tan return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * 474177ba1f9SLey Foon Tan (1 + denom) - 1; 475177ba1f9SLey Foon Tan } 476177ba1f9SLey Foon Tan 477177ba1f9SLey Foon Tan /* 478177ba1f9SLey Foon Tan * Calculate the new PLL numerator which is based on existing DTS hand off and 479177ba1f9SLey Foon Tan * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the 480177ba1f9SLey Foon Tan * numerator while maintaining denominator as denominator will influence the 481177ba1f9SLey Foon Tan * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final 482177ba1f9SLey Foon Tan * value for numerator is minus with 1 to cater our register value 483177ba1f9SLey Foon Tan * representation. 484177ba1f9SLey Foon Tan */ 485177ba1f9SLey Foon Tan static unsigned int cm_calc_safe_pll_numer(int main0periph1, 486177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 487177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 488177ba1f9SLey Foon Tan unsigned int safe_hz) 489177ba1f9SLey Foon Tan { 490177ba1f9SLey Foon Tan unsigned int clk_hz = 0; 491177ba1f9SLey Foon Tan 492177ba1f9SLey Foon Tan /* Check for main PLL */ 493177ba1f9SLey Foon Tan if (main0periph1 == 0) { 494177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 495177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 496177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 497177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 498177ba1f9SLey Foon Tan break; 499177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 500177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 501177ba1f9SLey Foon Tan break; 502177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 503177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 504177ba1f9SLey Foon Tan break; 505177ba1f9SLey Foon Tan default: 506177ba1f9SLey Foon Tan return 0; 507177ba1f9SLey Foon Tan } 508177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 509177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ 510177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 511177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 512177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 513177ba1f9SLey Foon Tan break; 514177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 515177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 516177ba1f9SLey Foon Tan break; 517177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 518177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 519177ba1f9SLey Foon Tan break; 520177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 521177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 522177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 523177ba1f9SLey Foon Tan break; 524177ba1f9SLey Foon Tan default: 525177ba1f9SLey Foon Tan return 0; 526177ba1f9SLey Foon Tan } 527177ba1f9SLey Foon Tan } else { 528177ba1f9SLey Foon Tan return 0; 529177ba1f9SLey Foon Tan } 530177ba1f9SLey Foon Tan 531177ba1f9SLey Foon Tan return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); 532177ba1f9SLey Foon Tan } 533177ba1f9SLey Foon Tan 534177ba1f9SLey Foon Tan /* ramping the main PLL to final value */ 535177ba1f9SLey Foon Tan static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, 536177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 537177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz) 538177ba1f9SLey Foon Tan { 539177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 540177ba1f9SLey Foon Tan 541177ba1f9SLey Foon Tan /* find out the increment value */ 542177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 543177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 544177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 545177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 546177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 547177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 548177ba1f9SLey Foon Tan } 549177ba1f9SLey Foon Tan 550177ba1f9SLey Foon Tan /* execute the ramping here */ 551177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_main_hz + clk_incr_hz; 552177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 553177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << 554177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 555177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), 556177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 557177ba1f9SLey Foon Tan mdelay(1); 558177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 559177ba1f9SLey Foon Tan } 560177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 561177ba1f9SLey Foon Tan main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); 562177ba1f9SLey Foon Tan mdelay(1); 563177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 564177ba1f9SLey Foon Tan } 565177ba1f9SLey Foon Tan 566177ba1f9SLey Foon Tan /* ramping the periph PLL to final value */ 567177ba1f9SLey Foon Tan static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, 568177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 569177ba1f9SLey Foon Tan unsigned int pll_ramp_periph_hz) 570177ba1f9SLey Foon Tan { 571177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 572177ba1f9SLey Foon Tan 573177ba1f9SLey Foon Tan /* find out the increment value */ 574177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 575177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 576177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 577177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 578177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 579177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 580177ba1f9SLey Foon Tan } 581177ba1f9SLey Foon Tan /* execute the ramping here */ 582177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; 583177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 584177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 585177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), 586177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 587177ba1f9SLey Foon Tan mdelay(1); 588177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 589177ba1f9SLey Foon Tan } 590177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 591177ba1f9SLey Foon Tan per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); 592177ba1f9SLey Foon Tan mdelay(1); 593177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 594177ba1f9SLey Foon Tan } 595177ba1f9SLey Foon Tan 596177ba1f9SLey Foon Tan /* 597177ba1f9SLey Foon Tan * Setup clocks while making no assumptions of the 598177ba1f9SLey Foon Tan * previous state of the clocks. 599177ba1f9SLey Foon Tan * 600177ba1f9SLey Foon Tan * Start by being paranoid and gate all sw managed clocks 601177ba1f9SLey Foon Tan * 602177ba1f9SLey Foon Tan * Put all plls in bypass 603177ba1f9SLey Foon Tan * 604177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value (bgpwr dwn). 605177ba1f9SLey Foon Tan * 606177ba1f9SLey Foon Tan * Put peripheral and main pll src to reset value to avoid glitch. 607177ba1f9SLey Foon Tan * 608177ba1f9SLey Foon Tan * Delay 5 us. 609177ba1f9SLey Foon Tan * 610177ba1f9SLey Foon Tan * Deassert bg pwr dn and set numerator and denominator 611177ba1f9SLey Foon Tan * 612177ba1f9SLey Foon Tan * Start 7 us timer. 613177ba1f9SLey Foon Tan * 614177ba1f9SLey Foon Tan * set internal dividers 615177ba1f9SLey Foon Tan * 616177ba1f9SLey Foon Tan * Wait for 7 us timer. 617177ba1f9SLey Foon Tan * 618177ba1f9SLey Foon Tan * Enable plls 619177ba1f9SLey Foon Tan * 620177ba1f9SLey Foon Tan * Set external dividers while plls are locking 621177ba1f9SLey Foon Tan * 622177ba1f9SLey Foon Tan * Wait for pll lock 623177ba1f9SLey Foon Tan * 624177ba1f9SLey Foon Tan * Assert/deassert outreset all. 625177ba1f9SLey Foon Tan * 626177ba1f9SLey Foon Tan * Take all pll's out of bypass 627177ba1f9SLey Foon Tan * 628177ba1f9SLey Foon Tan * Clear safe mode 629177ba1f9SLey Foon Tan * 630177ba1f9SLey Foon Tan * set source main and peripheral clocks 631177ba1f9SLey Foon Tan * 632177ba1f9SLey Foon Tan * Ungate clocks 633177ba1f9SLey Foon Tan */ 634177ba1f9SLey Foon Tan 635177ba1f9SLey Foon Tan static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 636177ba1f9SLey Foon Tan { 637177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, 638177ba1f9SLey Foon Tan ramp_required; 639177ba1f9SLey Foon Tan 640177ba1f9SLey Foon Tan /* gate off all mainpll clock excpet HW managed clock */ 641177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 642177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 643177ba1f9SLey Foon Tan &clock_manager_base->main_pll.enr); 644177ba1f9SLey Foon Tan 645177ba1f9SLey Foon Tan /* now we can gate off the rest of the peripheral clocks */ 646177ba1f9SLey Foon Tan writel(0, &clock_manager_base->per_pll.en); 647177ba1f9SLey Foon Tan 648177ba1f9SLey Foon Tan /* Put all plls in external bypass */ 649177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 650177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypasss); 651177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 652177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypasss); 653177ba1f9SLey Foon Tan 654177ba1f9SLey Foon Tan /* 655177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value. 656177ba1f9SLey Foon Tan * Some code might have messed with them. At same time set the 657177ba1f9SLey Foon Tan * desired clock source 658177ba1f9SLey Foon Tan */ 659177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO0_RESET | 660177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | 661177ba1f9SLey Foon Tan (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), 662177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 663177ba1f9SLey Foon Tan 664177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO0_RESET | 665177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | 666177ba1f9SLey Foon Tan (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), 667177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 668177ba1f9SLey Foon Tan 669177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); 670177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); 671177ba1f9SLey Foon Tan 672177ba1f9SLey Foon Tan /* clear the interrupt register status register */ 673177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 674177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 675177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 676177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 677177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 678177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | 679177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | 680177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, 681177ba1f9SLey Foon Tan &clock_manager_base->intr); 682177ba1f9SLey Foon Tan 683177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for main PLL */ 684177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); 685177ba1f9SLey Foon Tan if (ramp_required) { 686177ba1f9SLey Foon Tan /* set main PLL to safe starting threshold frequency */ 687177ba1f9SLey Foon Tan if (ramp_required == 1) 688177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 689177ba1f9SLey Foon Tan else if (ramp_required == 2) 690177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 691177ba1f9SLey Foon Tan 692177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 693177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, 694177ba1f9SLey Foon Tan pll_ramp_main_hz), 695177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 696177ba1f9SLey Foon Tan } else 697177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 698177ba1f9SLey Foon Tan main_cfg->vco1_numer, 699177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 700177ba1f9SLey Foon Tan 701177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for periph PLL */ 702177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); 703177ba1f9SLey Foon Tan if (ramp_required) { 704177ba1f9SLey Foon Tan /* set periph PLL to safe starting threshold frequency */ 705177ba1f9SLey Foon Tan if (ramp_required == 1) 706177ba1f9SLey Foon Tan pll_ramp_periph_hz = 707177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 708177ba1f9SLey Foon Tan else if (ramp_required == 2) 709177ba1f9SLey Foon Tan pll_ramp_periph_hz = 710177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 711177ba1f9SLey Foon Tan 712177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 713177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, 714177ba1f9SLey Foon Tan pll_ramp_periph_hz), 715177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 716177ba1f9SLey Foon Tan } else 717177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 718177ba1f9SLey Foon Tan per_cfg->vco1_numer, 719177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 720177ba1f9SLey Foon Tan 721177ba1f9SLey Foon Tan /* Wait for at least 5 us */ 722177ba1f9SLey Foon Tan udelay(5); 723177ba1f9SLey Foon Tan 724177ba1f9SLey Foon Tan /* Now deassert BGPWRDN and PWRDN */ 725177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 726177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | 727177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); 728177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 729177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | 730177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); 731177ba1f9SLey Foon Tan 732177ba1f9SLey Foon Tan /* Wait for at least 7 us */ 733177ba1f9SLey Foon Tan udelay(7); 734177ba1f9SLey Foon Tan 735177ba1f9SLey Foon Tan /* enable the VCO and disable the external regulator to PLL */ 736177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->main_pll.vco0) & 737177ba1f9SLey Foon Tan ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | 738177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_EN_SET_MSK, 739177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 740177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->per_pll.vco0) & 741177ba1f9SLey Foon Tan ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | 742177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_EN_SET_MSK, 743177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 744177ba1f9SLey Foon Tan 745177ba1f9SLey Foon Tan /* setup all the main PLL counter and clock source */ 746177ba1f9SLey Foon Tan writel(main_cfg->nocclk, 747177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); 748177ba1f9SLey Foon Tan writel(main_cfg->mpuclk, 749177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); 750177ba1f9SLey Foon Tan 751177ba1f9SLey Foon Tan /* main_emaca_clk divider */ 752177ba1f9SLey Foon Tan writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); 753177ba1f9SLey Foon Tan /* main_emacb_clk divider */ 754177ba1f9SLey Foon Tan writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); 755177ba1f9SLey Foon Tan /* main_emac_ptp_clk divider */ 756177ba1f9SLey Foon Tan writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); 757177ba1f9SLey Foon Tan /* main_gpio_db_clk divider */ 758177ba1f9SLey Foon Tan writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); 759177ba1f9SLey Foon Tan /* main_sdmmc_clk divider */ 760177ba1f9SLey Foon Tan writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); 761177ba1f9SLey Foon Tan /* main_s2f_user0_clk divider */ 762177ba1f9SLey Foon Tan writel(main_cfg->cntr7clk_cnt | 763177ba1f9SLey Foon Tan (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), 764177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr7clk); 765177ba1f9SLey Foon Tan /* main_s2f_user1_clk divider */ 766177ba1f9SLey Foon Tan writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); 767177ba1f9SLey Foon Tan /* main_hmc_pll_clk divider */ 768177ba1f9SLey Foon Tan writel(main_cfg->cntr9clk_cnt | 769177ba1f9SLey Foon Tan (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), 770177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr9clk); 771177ba1f9SLey Foon Tan /* main_periph_ref_clk divider */ 772177ba1f9SLey Foon Tan writel(main_cfg->cntr15clk_cnt, 773177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr15clk); 774177ba1f9SLey Foon Tan 775177ba1f9SLey Foon Tan /* setup all the peripheral PLL counter and clock source */ 776177ba1f9SLey Foon Tan /* peri_emaca_clk divider */ 777177ba1f9SLey Foon Tan writel(per_cfg->cntr2clk_cnt | 778177ba1f9SLey Foon Tan (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), 779177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr2clk); 780177ba1f9SLey Foon Tan /* peri_emacb_clk divider */ 781177ba1f9SLey Foon Tan writel(per_cfg->cntr3clk_cnt | 782177ba1f9SLey Foon Tan (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), 783177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr3clk); 784177ba1f9SLey Foon Tan /* peri_emac_ptp_clk divider */ 785177ba1f9SLey Foon Tan writel(per_cfg->cntr4clk_cnt | 786177ba1f9SLey Foon Tan (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), 787177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr4clk); 788177ba1f9SLey Foon Tan /* peri_gpio_db_clk divider */ 789177ba1f9SLey Foon Tan writel(per_cfg->cntr5clk_cnt | 790177ba1f9SLey Foon Tan (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), 791177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr5clk); 792177ba1f9SLey Foon Tan /* peri_sdmmc_clk divider */ 793177ba1f9SLey Foon Tan writel(per_cfg->cntr6clk_cnt | 794177ba1f9SLey Foon Tan (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), 795177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr6clk); 796177ba1f9SLey Foon Tan /* peri_s2f_user0_clk divider */ 797177ba1f9SLey Foon Tan writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); 798177ba1f9SLey Foon Tan /* peri_s2f_user1_clk divider */ 799177ba1f9SLey Foon Tan writel(per_cfg->cntr8clk_cnt | 800177ba1f9SLey Foon Tan (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), 801177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr8clk); 802177ba1f9SLey Foon Tan /* peri_hmc_pll_clk divider */ 803177ba1f9SLey Foon Tan writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); 804177ba1f9SLey Foon Tan 805177ba1f9SLey Foon Tan /* setup all the external PLL counter */ 806177ba1f9SLey Foon Tan /* mpu wrapper / external divider */ 807177ba1f9SLey Foon Tan writel(main_cfg->mpuclk_cnt | 808177ba1f9SLey Foon Tan (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), 809177ba1f9SLey Foon Tan &clock_manager_base->main_pll.mpuclk); 810177ba1f9SLey Foon Tan /* NOC wrapper / external divider */ 811177ba1f9SLey Foon Tan writel(main_cfg->nocclk_cnt | 812177ba1f9SLey Foon Tan (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), 813177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocclk); 814177ba1f9SLey Foon Tan /* NOC subclock divider such as l4 */ 815177ba1f9SLey Foon Tan writel(main_cfg->nocdiv_l4mainclk | 816177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4mpclk << 817177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | 818177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4spclk << 819177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | 820177ba1f9SLey Foon Tan (main_cfg->nocdiv_csatclk << 821177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | 822177ba1f9SLey Foon Tan (main_cfg->nocdiv_cstraceclk << 823177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | 824177ba1f9SLey Foon Tan (main_cfg->nocdiv_cspdbclk << 825177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), 826177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocdiv); 827177ba1f9SLey Foon Tan /* gpio_db external divider */ 828177ba1f9SLey Foon Tan writel(per_cfg->gpiodiv_gpiodbclk, 829177ba1f9SLey Foon Tan &clock_manager_base->per_pll.gpiodiv); 830177ba1f9SLey Foon Tan 831177ba1f9SLey Foon Tan /* setup the EMAC clock mux select */ 832177ba1f9SLey Foon Tan writel((per_cfg->emacctl_emac0sel << 833177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | 834177ba1f9SLey Foon Tan (per_cfg->emacctl_emac1sel << 835177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | 836177ba1f9SLey Foon Tan (per_cfg->emacctl_emac2sel << 837177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), 838177ba1f9SLey Foon Tan &clock_manager_base->per_pll.emacctl); 839177ba1f9SLey Foon Tan 840177ba1f9SLey Foon Tan /* at this stage, check for PLL lock status */ 841177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 842177ba1f9SLey Foon Tan 843177ba1f9SLey Foon Tan /* 844177ba1f9SLey Foon Tan * after locking, but before taking out of bypass, 845177ba1f9SLey Foon Tan * assert/deassert outresetall 846177ba1f9SLey Foon Tan */ 847177ba1f9SLey Foon Tan /* assert mainpll outresetall */ 848177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->main_pll.vco0, 849177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 850177ba1f9SLey Foon Tan /* assert perpll outresetall */ 851177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->per_pll.vco0, 852177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 853177ba1f9SLey Foon Tan /* de-assert mainpll outresetall */ 854177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 855177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 856177ba1f9SLey Foon Tan /* de-assert perpll outresetall */ 857177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 858177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 859177ba1f9SLey Foon Tan 860177ba1f9SLey Foon Tan /* Take all PLLs out of bypass when boot mode is cleared. */ 861177ba1f9SLey Foon Tan /* release mainpll from bypass */ 862177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 863177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypassr); 864177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 865177ba1f9SLey Foon Tan cm_wait_for_fsm(); 866177ba1f9SLey Foon Tan 867177ba1f9SLey Foon Tan /* release perpll from bypass */ 868177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 869177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypassr); 870177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 871177ba1f9SLey Foon Tan cm_wait_for_fsm(); 872177ba1f9SLey Foon Tan 873177ba1f9SLey Foon Tan /* clear boot mode */ 874177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->ctrl, 875177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); 876177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 877177ba1f9SLey Foon Tan cm_wait_for_fsm(); 878177ba1f9SLey Foon Tan 879177ba1f9SLey Foon Tan /* At here, we need to ramp to final value if needed */ 880177ba1f9SLey Foon Tan if (pll_ramp_main_hz != 0) 881177ba1f9SLey Foon Tan cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); 882177ba1f9SLey Foon Tan if (pll_ramp_periph_hz != 0) 883177ba1f9SLey Foon Tan cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); 884177ba1f9SLey Foon Tan 885177ba1f9SLey Foon Tan /* Now ungate non-hw-managed clocks */ 886177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 887177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 888177ba1f9SLey Foon Tan &clock_manager_base->main_pll.ens); 889177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); 890177ba1f9SLey Foon Tan 891177ba1f9SLey Foon Tan /* Clear the loss lock and slip bits as they might set during 892177ba1f9SLey Foon Tan clock reconfiguration */ 893177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 894177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 895177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 896177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 897177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 898177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, 899177ba1f9SLey Foon Tan &clock_manager_base->intr); 900177ba1f9SLey Foon Tan 901177ba1f9SLey Foon Tan return 0; 902177ba1f9SLey Foon Tan } 903177ba1f9SLey Foon Tan 904177ba1f9SLey Foon Tan void cm_use_intosc(void) 905177ba1f9SLey Foon Tan { 906177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->ctrl, 907177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); 908177ba1f9SLey Foon Tan } 909177ba1f9SLey Foon Tan 910177ba1f9SLey Foon Tan unsigned int cm_get_noc_clk_hz(void) 911177ba1f9SLey Foon Tan { 912177ba1f9SLey Foon Tan unsigned int clk_src, divisor, nocclk, src_hz; 913177ba1f9SLey Foon Tan 914177ba1f9SLey Foon Tan nocclk = readl(&clock_manager_base->main_pll.nocclk); 915177ba1f9SLey Foon Tan clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & 916177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_SRC_MSK; 917177ba1f9SLey Foon Tan 918177ba1f9SLey Foon Tan divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK); 919177ba1f9SLey Foon Tan 920177ba1f9SLey Foon Tan if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { 921177ba1f9SLey Foon Tan src_hz = cm_get_main_vco_clk_hz(); 922177ba1f9SLey Foon Tan src_hz /= 1 + 923177ba1f9SLey Foon Tan (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) & 924177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 925177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { 926177ba1f9SLey Foon Tan src_hz = cm_get_per_vco_clk_hz(); 927177ba1f9SLey Foon Tan src_hz /= 1 + 928177ba1f9SLey Foon Tan ((readl(SOCFPGA_CLKMGR_ADDRESS + 929177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOC_CLK_OFFSET) >> 930177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 931177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 932177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { 933177ba1f9SLey Foon Tan src_hz = eosc1_hz; 934177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { 935177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 936177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { 937177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 938177ba1f9SLey Foon Tan } else { 939177ba1f9SLey Foon Tan src_hz = 0; 940177ba1f9SLey Foon Tan } 941177ba1f9SLey Foon Tan 942177ba1f9SLey Foon Tan return src_hz / divisor; 943177ba1f9SLey Foon Tan } 944177ba1f9SLey Foon Tan 945177ba1f9SLey Foon Tan unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift) 946177ba1f9SLey Foon Tan { 947177ba1f9SLey Foon Tan unsigned int divisor2 = 1 << 948177ba1f9SLey Foon Tan ((readl(&clock_manager_base->main_pll.nocdiv) >> 949177ba1f9SLey Foon Tan nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK); 950177ba1f9SLey Foon Tan 951177ba1f9SLey Foon Tan return cm_get_noc_clk_hz() / divisor2; 952177ba1f9SLey Foon Tan } 953177ba1f9SLey Foon Tan 954177ba1f9SLey Foon Tan int cm_basic_init(const void *blob) 955177ba1f9SLey Foon Tan { 956177ba1f9SLey Foon Tan struct mainpll_cfg main_cfg; 957177ba1f9SLey Foon Tan struct perpll_cfg per_cfg; 958177ba1f9SLey Foon Tan int rval; 959177ba1f9SLey Foon Tan 960177ba1f9SLey Foon Tan /* initialize to zero for use case of optional node */ 961177ba1f9SLey Foon Tan memset(&main_cfg, 0, sizeof(main_cfg)); 962177ba1f9SLey Foon Tan memset(&per_cfg, 0, sizeof(per_cfg)); 963177ba1f9SLey Foon Tan 964480f7f9cSMarek Vasut rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); 965177ba1f9SLey Foon Tan if (rval) 966177ba1f9SLey Foon Tan return rval; 967177ba1f9SLey Foon Tan 968177ba1f9SLey Foon Tan rval = cm_full_cfg(&main_cfg, &per_cfg); 969177ba1f9SLey Foon Tan 970177ba1f9SLey Foon Tan cm_l4_main_clk_hz = 971177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 972177ba1f9SLey Foon Tan 973177ba1f9SLey Foon Tan cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 974177ba1f9SLey Foon Tan 975177ba1f9SLey Foon Tan cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz(); 976177ba1f9SLey Foon Tan 977177ba1f9SLey Foon Tan cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4; 978177ba1f9SLey Foon Tan 979177ba1f9SLey Foon Tan return rval; 980177ba1f9SLey Foon Tan } 981177ba1f9SLey Foon Tan 982177ba1f9SLey Foon Tan unsigned long cm_get_mpu_clk_hz(void) 983177ba1f9SLey Foon Tan { 984177ba1f9SLey Foon Tan u32 reg, clk_hz; 985177ba1f9SLey Foon Tan u32 clk_src, mainmpuclk_reg; 986177ba1f9SLey Foon Tan 987177ba1f9SLey Foon Tan mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); 988177ba1f9SLey Foon Tan 989177ba1f9SLey Foon Tan clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & 990177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_SRC_MSK; 991177ba1f9SLey Foon Tan 992177ba1f9SLey Foon Tan reg = readl(&clock_manager_base->altera.mpuclk); 993177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 994177ba1f9SLey Foon Tan switch (clk_src) { 995177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 996177ba1f9SLey Foon Tan clk_hz = cm_get_main_vco_clk_hz(); 997177ba1f9SLey Foon Tan clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 998177ba1f9SLey Foon Tan break; 999177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 1000177ba1f9SLey Foon Tan clk_hz = cm_get_per_vco_clk_hz(); 1001177ba1f9SLey Foon Tan clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 1002177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); 1003177ba1f9SLey Foon Tan break; 1004177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 1005177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 1006177ba1f9SLey Foon Tan break; 1007177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 1008177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 1009177ba1f9SLey Foon Tan break; 1010177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 1011177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 1012177ba1f9SLey Foon Tan break; 1013177ba1f9SLey Foon Tan default: 1014177ba1f9SLey Foon Tan printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src); 1015177ba1f9SLey Foon Tan return 0; 1016177ba1f9SLey Foon Tan } 1017177ba1f9SLey Foon Tan 1018177ba1f9SLey Foon Tan clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 1019177ba1f9SLey Foon Tan 1020177ba1f9SLey Foon Tan return clk_hz; 1021177ba1f9SLey Foon Tan } 1022177ba1f9SLey Foon Tan 1023177ba1f9SLey Foon Tan unsigned int cm_get_per_vco_clk_hz(void) 1024177ba1f9SLey Foon Tan { 1025177ba1f9SLey Foon Tan u32 src_hz = 0; 1026177ba1f9SLey Foon Tan u32 clk_src = 0; 1027177ba1f9SLey Foon Tan u32 numer = 0; 1028177ba1f9SLey Foon Tan u32 denom = 0; 1029177ba1f9SLey Foon Tan u32 vco = 0; 1030177ba1f9SLey Foon Tan 1031177ba1f9SLey Foon Tan clk_src = readl(&clock_manager_base->per_pll.vco0); 1032177ba1f9SLey Foon Tan 1033177ba1f9SLey Foon Tan clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) & 1034177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PSRC_MSK; 1035177ba1f9SLey Foon Tan 1036177ba1f9SLey Foon Tan if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) { 1037177ba1f9SLey Foon Tan src_hz = eosc1_hz; 1038177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) { 1039177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 1040177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) { 1041177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 1042177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) { 1043177ba1f9SLey Foon Tan src_hz = cm_get_main_vco_clk_hz(); 1044177ba1f9SLey Foon Tan src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) & 1045177ba1f9SLey Foon Tan CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; 1046177ba1f9SLey Foon Tan } else { 1047177ba1f9SLey Foon Tan printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src); 1048177ba1f9SLey Foon Tan return 0; 1049177ba1f9SLey Foon Tan } 1050177ba1f9SLey Foon Tan 1051177ba1f9SLey Foon Tan vco = readl(&clock_manager_base->per_pll.vco1); 1052177ba1f9SLey Foon Tan 1053177ba1f9SLey Foon Tan numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; 1054177ba1f9SLey Foon Tan 1055177ba1f9SLey Foon Tan denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & 1056177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO1_DENOM_MSK; 1057177ba1f9SLey Foon Tan 1058177ba1f9SLey Foon Tan vco = src_hz; 1059177ba1f9SLey Foon Tan vco /= 1 + denom; 1060177ba1f9SLey Foon Tan vco *= 1 + numer; 1061177ba1f9SLey Foon Tan 1062177ba1f9SLey Foon Tan return vco; 1063177ba1f9SLey Foon Tan } 1064177ba1f9SLey Foon Tan 1065177ba1f9SLey Foon Tan unsigned int cm_get_main_vco_clk_hz(void) 1066177ba1f9SLey Foon Tan { 1067177ba1f9SLey Foon Tan u32 src_hz, numer, denom, vco; 1068177ba1f9SLey Foon Tan 1069177ba1f9SLey Foon Tan u32 clk_src = readl(&clock_manager_base->main_pll.vco0); 1070177ba1f9SLey Foon Tan 1071177ba1f9SLey Foon Tan clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) & 1072177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PSRC_MSK; 1073177ba1f9SLey Foon Tan 1074177ba1f9SLey Foon Tan if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) { 1075177ba1f9SLey Foon Tan src_hz = eosc1_hz; 1076177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) { 1077177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 1078177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) { 1079177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 1080177ba1f9SLey Foon Tan } else { 1081177ba1f9SLey Foon Tan printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src); 1082177ba1f9SLey Foon Tan return 0; 1083177ba1f9SLey Foon Tan } 1084177ba1f9SLey Foon Tan 1085177ba1f9SLey Foon Tan vco = readl(&clock_manager_base->main_pll.vco1); 1086177ba1f9SLey Foon Tan 1087177ba1f9SLey Foon Tan numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK; 1088177ba1f9SLey Foon Tan 1089177ba1f9SLey Foon Tan denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & 1090177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_MSK; 1091177ba1f9SLey Foon Tan 1092177ba1f9SLey Foon Tan vco = src_hz; 1093177ba1f9SLey Foon Tan vco /= 1 + denom; 1094177ba1f9SLey Foon Tan vco *= 1 + numer; 1095177ba1f9SLey Foon Tan 1096177ba1f9SLey Foon Tan return vco; 1097177ba1f9SLey Foon Tan } 1098177ba1f9SLey Foon Tan 1099177ba1f9SLey Foon Tan unsigned int cm_get_l4_sp_clk_hz(void) 1100177ba1f9SLey Foon Tan { 1101177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB); 1102177ba1f9SLey Foon Tan } 1103177ba1f9SLey Foon Tan 1104177ba1f9SLey Foon Tan unsigned int cm_get_mmc_controller_clk_hz(void) 1105177ba1f9SLey Foon Tan { 1106177ba1f9SLey Foon Tan u32 clk_hz = 0; 1107177ba1f9SLey Foon Tan u32 clk_input = 0; 1108177ba1f9SLey Foon Tan 1109177ba1f9SLey Foon Tan clk_input = readl(&clock_manager_base->per_pll.cntr6clk); 1110177ba1f9SLey Foon Tan clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & 1111177ba1f9SLey Foon Tan CLKMGR_PERPLLGRP_SRC_MSK; 1112177ba1f9SLey Foon Tan 1113177ba1f9SLey Foon Tan switch (clk_input) { 1114177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_MAIN: 1115177ba1f9SLey Foon Tan clk_hz = cm_get_main_vco_clk_hz(); 1116177ba1f9SLey Foon Tan clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & 1117177ba1f9SLey Foon Tan CLKMGR_MAINPLL_CNTRCLK_MSK); 1118177ba1f9SLey Foon Tan break; 1119177ba1f9SLey Foon Tan 1120177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_PERI: 1121177ba1f9SLey Foon Tan clk_hz = cm_get_per_vco_clk_hz(); 1122177ba1f9SLey Foon Tan clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & 1123177ba1f9SLey Foon Tan CLKMGR_PERPLL_CNTRCLK_MSK); 1124177ba1f9SLey Foon Tan break; 1125177ba1f9SLey Foon Tan 1126177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_OSC1: 1127177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 1128177ba1f9SLey Foon Tan break; 1129177ba1f9SLey Foon Tan 1130177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_INTOSC: 1131177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 1132177ba1f9SLey Foon Tan break; 1133177ba1f9SLey Foon Tan 1134177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_FPGA: 1135177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 1136177ba1f9SLey Foon Tan break; 1137177ba1f9SLey Foon Tan } 1138177ba1f9SLey Foon Tan 1139177ba1f9SLey Foon Tan return clk_hz / 4; 1140177ba1f9SLey Foon Tan } 1141177ba1f9SLey Foon Tan 1142177ba1f9SLey Foon Tan unsigned int cm_get_spi_controller_clk_hz(void) 1143177ba1f9SLey Foon Tan { 1144177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 1145177ba1f9SLey Foon Tan } 1146177ba1f9SLey Foon Tan 1147177ba1f9SLey Foon Tan unsigned int cm_get_qspi_controller_clk_hz(void) 1148177ba1f9SLey Foon Tan { 1149177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 1150177ba1f9SLey Foon Tan } 1151177ba1f9SLey Foon Tan 115221143ce1SEugeniy Paltsev /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ 115321143ce1SEugeniy Paltsev int dw_spi_get_clk(struct udevice *bus, ulong *rate) 115421143ce1SEugeniy Paltsev { 115521143ce1SEugeniy Paltsev *rate = cm_get_spi_controller_clk_hz(); 115621143ce1SEugeniy Paltsev 115721143ce1SEugeniy Paltsev return 0; 115821143ce1SEugeniy Paltsev } 115921143ce1SEugeniy Paltsev 1160177ba1f9SLey Foon Tan void cm_print_clock_quick_summary(void) 1161177ba1f9SLey Foon Tan { 1162177ba1f9SLey Foon Tan printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); 1163177ba1f9SLey Foon Tan printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); 1164177ba1f9SLey Foon Tan printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); 1165177ba1f9SLey Foon Tan printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); 1166177ba1f9SLey Foon Tan printf("EOSC1 %8d kHz\n", eosc1_hz / 1000); 1167177ba1f9SLey Foon Tan printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000); 1168177ba1f9SLey Foon Tan printf("f2s_free %8d kHz\n", f2s_free_hz / 1000); 1169177ba1f9SLey Foon Tan printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000); 1170177ba1f9SLey Foon Tan printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000); 1171177ba1f9SLey Foon Tan printf("L4 Main %8d kHz\n", 1172177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000); 1173177ba1f9SLey Foon Tan printf("L4 MP %8d kHz\n", 1174177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000); 1175177ba1f9SLey Foon Tan printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); 1176177ba1f9SLey Foon Tan printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000); 1177177ba1f9SLey Foon Tan } 1178