1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2177ba1f9SLey Foon Tan /* 3177ba1f9SLey Foon Tan * Copyright (C) 2016-2017 Intel Corporation 4177ba1f9SLey Foon Tan */ 5177ba1f9SLey Foon Tan 6177ba1f9SLey Foon Tan #include <common.h> 7177ba1f9SLey Foon Tan #include <fdtdec.h> 8177ba1f9SLey Foon Tan #include <asm/io.h> 921143ce1SEugeniy Paltsev #include <dm.h> 10177ba1f9SLey Foon Tan #include <asm/arch/clock_manager.h> 11177ba1f9SLey Foon Tan 12177ba1f9SLey Foon Tan static u32 eosc1_hz; 13177ba1f9SLey Foon Tan static u32 cb_intosc_hz; 14177ba1f9SLey Foon Tan static u32 f2s_free_hz; 15177ba1f9SLey Foon Tan static u32 cm_l4_main_clk_hz; 16177ba1f9SLey Foon Tan static u32 cm_l4_sp_clk_hz; 17177ba1f9SLey Foon Tan static u32 cm_l4_mp_clk_hz; 18177ba1f9SLey Foon Tan static u32 cm_l4_sys_free_clk_hz; 19177ba1f9SLey Foon Tan 20177ba1f9SLey Foon Tan struct mainpll_cfg { 21177ba1f9SLey Foon Tan u32 vco0_psrc; 22177ba1f9SLey Foon Tan u32 vco1_denom; 23177ba1f9SLey Foon Tan u32 vco1_numer; 24177ba1f9SLey Foon Tan u32 mpuclk; 25177ba1f9SLey Foon Tan u32 mpuclk_cnt; 26177ba1f9SLey Foon Tan u32 mpuclk_src; 27177ba1f9SLey Foon Tan u32 nocclk; 28177ba1f9SLey Foon Tan u32 nocclk_cnt; 29177ba1f9SLey Foon Tan u32 nocclk_src; 30177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 31177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 32177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 33177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 34177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 35177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 36177ba1f9SLey Foon Tan u32 cntr7clk_src; 37177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 38177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 39177ba1f9SLey Foon Tan u32 cntr9clk_src; 40177ba1f9SLey Foon Tan u32 cntr15clk_cnt; 41177ba1f9SLey Foon Tan u32 nocdiv_l4mainclk; 42177ba1f9SLey Foon Tan u32 nocdiv_l4mpclk; 43177ba1f9SLey Foon Tan u32 nocdiv_l4spclk; 44177ba1f9SLey Foon Tan u32 nocdiv_csatclk; 45177ba1f9SLey Foon Tan u32 nocdiv_cstraceclk; 46177ba1f9SLey Foon Tan u32 nocdiv_cspdbclk; 47177ba1f9SLey Foon Tan }; 48177ba1f9SLey Foon Tan 49177ba1f9SLey Foon Tan struct perpll_cfg { 50177ba1f9SLey Foon Tan u32 vco0_psrc; 51177ba1f9SLey Foon Tan u32 vco1_denom; 52177ba1f9SLey Foon Tan u32 vco1_numer; 53177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 54177ba1f9SLey Foon Tan u32 cntr2clk_src; 55177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 56177ba1f9SLey Foon Tan u32 cntr3clk_src; 57177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 58177ba1f9SLey Foon Tan u32 cntr4clk_src; 59177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 60177ba1f9SLey Foon Tan u32 cntr5clk_src; 61177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 62177ba1f9SLey Foon Tan u32 cntr6clk_src; 63177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 64177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 65177ba1f9SLey Foon Tan u32 cntr8clk_src; 66177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 67177ba1f9SLey Foon Tan u32 emacctl_emac0sel; 68177ba1f9SLey Foon Tan u32 emacctl_emac1sel; 69177ba1f9SLey Foon Tan u32 emacctl_emac2sel; 70177ba1f9SLey Foon Tan u32 gpiodiv_gpiodbclk; 71177ba1f9SLey Foon Tan }; 72177ba1f9SLey Foon Tan 73177ba1f9SLey Foon Tan struct alteragrp_cfg { 74177ba1f9SLey Foon Tan u32 nocclk; 75177ba1f9SLey Foon Tan u32 mpuclk; 76177ba1f9SLey Foon Tan }; 77177ba1f9SLey Foon Tan 78177ba1f9SLey Foon Tan static const struct socfpga_clock_manager *clock_manager_base = 79177ba1f9SLey Foon Tan (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 80177ba1f9SLey Foon Tan 81177ba1f9SLey Foon Tan static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) 82177ba1f9SLey Foon Tan { 83177ba1f9SLey Foon Tan if (fdtdec_get_int_array(blob, node, "altr,of_reg_value", 84177ba1f9SLey Foon Tan (u32 *)cfg, cfg_len)) { 85177ba1f9SLey Foon Tan /* could not find required property */ 86177ba1f9SLey Foon Tan return -EINVAL; 87177ba1f9SLey Foon Tan } 88177ba1f9SLey Foon Tan 89177ba1f9SLey Foon Tan return 0; 90177ba1f9SLey Foon Tan } 91177ba1f9SLey Foon Tan 92177ba1f9SLey Foon Tan static int of_get_input_clks(const void *blob, int node, u32 *val) 93177ba1f9SLey Foon Tan { 94177ba1f9SLey Foon Tan *val = fdtdec_get_uint(blob, node, "clock-frequency", 0); 95177ba1f9SLey Foon Tan if (!*val) 96177ba1f9SLey Foon Tan return -EINVAL; 97177ba1f9SLey Foon Tan 98177ba1f9SLey Foon Tan return 0; 99177ba1f9SLey Foon Tan } 100177ba1f9SLey Foon Tan 101177ba1f9SLey Foon Tan static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, 102177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 103177ba1f9SLey Foon Tan struct alteragrp_cfg *altrgrp_cfg) 104177ba1f9SLey Foon Tan { 105177ba1f9SLey Foon Tan int node, child, len; 106177ba1f9SLey Foon Tan const char *node_name; 107177ba1f9SLey Foon Tan 108177ba1f9SLey Foon Tan node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK); 109177ba1f9SLey Foon Tan if (node < 0) 110177ba1f9SLey Foon Tan return -EINVAL; 111177ba1f9SLey Foon Tan 112177ba1f9SLey Foon Tan child = fdt_first_subnode(blob, node); 113177ba1f9SLey Foon Tan if (child < 0) 114177ba1f9SLey Foon Tan return -EINVAL; 115177ba1f9SLey Foon Tan 116177ba1f9SLey Foon Tan child = fdt_first_subnode(blob, child); 117177ba1f9SLey Foon Tan if (child < 0) 118177ba1f9SLey Foon Tan return -EINVAL; 119177ba1f9SLey Foon Tan 120177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 121177ba1f9SLey Foon Tan 122177ba1f9SLey Foon Tan while (node_name) { 123177ba1f9SLey Foon Tan if (!strcmp(node_name, "osc1")) { 124177ba1f9SLey Foon Tan if (of_get_input_clks(blob, child, &eosc1_hz)) 125177ba1f9SLey Foon Tan return -EINVAL; 126177ba1f9SLey Foon Tan } else if (!strcmp(node_name, "cb_intosc_ls_clk")) { 127177ba1f9SLey Foon Tan if (of_get_input_clks(blob, child, &cb_intosc_hz)) 128177ba1f9SLey Foon Tan return -EINVAL; 129177ba1f9SLey Foon Tan } else if (!strcmp(node_name, "f2s_free_clk")) { 130177ba1f9SLey Foon Tan if (of_get_input_clks(blob, child, &f2s_free_hz)) 131177ba1f9SLey Foon Tan return -EINVAL; 132177ba1f9SLey Foon Tan } else if (!strcmp(node_name, "main_pll")) { 133177ba1f9SLey Foon Tan if (of_to_struct(blob, child, 134177ba1f9SLey Foon Tan sizeof(*main_cfg)/sizeof(u32), 135177ba1f9SLey Foon Tan main_cfg)) 136177ba1f9SLey Foon Tan return -EINVAL; 137177ba1f9SLey Foon Tan } else if (!strcmp(node_name, "periph_pll")) { 138177ba1f9SLey Foon Tan if (of_to_struct(blob, child, 139177ba1f9SLey Foon Tan sizeof(*per_cfg)/sizeof(u32), 140177ba1f9SLey Foon Tan per_cfg)) 141177ba1f9SLey Foon Tan return -EINVAL; 142177ba1f9SLey Foon Tan } else if (!strcmp(node_name, "altera")) { 143177ba1f9SLey Foon Tan if (of_to_struct(blob, child, 144177ba1f9SLey Foon Tan sizeof(*altrgrp_cfg)/sizeof(u32), 145177ba1f9SLey Foon Tan altrgrp_cfg)) 146177ba1f9SLey Foon Tan return -EINVAL; 147177ba1f9SLey Foon Tan 148177ba1f9SLey Foon Tan main_cfg->mpuclk = altrgrp_cfg->mpuclk; 149177ba1f9SLey Foon Tan main_cfg->nocclk = altrgrp_cfg->nocclk; 150177ba1f9SLey Foon Tan } 151177ba1f9SLey Foon Tan child = fdt_next_subnode(blob, child); 152177ba1f9SLey Foon Tan 153177ba1f9SLey Foon Tan if (child < 0) 154177ba1f9SLey Foon Tan break; 155177ba1f9SLey Foon Tan 156177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 157177ba1f9SLey Foon Tan } 158177ba1f9SLey Foon Tan 159177ba1f9SLey Foon Tan return 0; 160177ba1f9SLey Foon Tan } 161177ba1f9SLey Foon Tan 162177ba1f9SLey Foon Tan /* calculate the intended main VCO frequency based on handoff */ 163177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_main_vco_clk_hz 164177ba1f9SLey Foon Tan (struct mainpll_cfg *main_cfg) 165177ba1f9SLey Foon Tan { 166177ba1f9SLey Foon Tan unsigned int clk_hz; 167177ba1f9SLey Foon Tan 168177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 169177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 170177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 171177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 172177ba1f9SLey Foon Tan break; 173177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 174177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 175177ba1f9SLey Foon Tan break; 176177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 177177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 178177ba1f9SLey Foon Tan break; 179177ba1f9SLey Foon Tan default: 180177ba1f9SLey Foon Tan return 0; 181177ba1f9SLey Foon Tan } 182177ba1f9SLey Foon Tan 183177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 184177ba1f9SLey Foon Tan clk_hz /= 1 + main_cfg->vco1_denom; 185177ba1f9SLey Foon Tan clk_hz *= 1 + main_cfg->vco1_numer; 186177ba1f9SLey Foon Tan 187177ba1f9SLey Foon Tan return clk_hz; 188177ba1f9SLey Foon Tan } 189177ba1f9SLey Foon Tan 190177ba1f9SLey Foon Tan /* calculate the intended periph VCO frequency based on handoff */ 191177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_periph_vco_clk_hz( 192177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 193177ba1f9SLey Foon Tan { 194177ba1f9SLey Foon Tan unsigned int clk_hz; 195177ba1f9SLey Foon Tan 196177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ 197177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 198177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 199177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 200177ba1f9SLey Foon Tan break; 201177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 202177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 203177ba1f9SLey Foon Tan break; 204177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 205177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 206177ba1f9SLey Foon Tan break; 207177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 208177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 209177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 210177ba1f9SLey Foon Tan break; 211177ba1f9SLey Foon Tan default: 212177ba1f9SLey Foon Tan return 0; 213177ba1f9SLey Foon Tan } 214177ba1f9SLey Foon Tan 215177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 216177ba1f9SLey Foon Tan clk_hz /= 1 + per_cfg->vco1_denom; 217177ba1f9SLey Foon Tan clk_hz *= 1 + per_cfg->vco1_numer; 218177ba1f9SLey Foon Tan 219177ba1f9SLey Foon Tan return clk_hz; 220177ba1f9SLey Foon Tan } 221177ba1f9SLey Foon Tan 222177ba1f9SLey Foon Tan /* calculate the intended MPU clock frequency based on handoff */ 223177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, 224177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 225177ba1f9SLey Foon Tan { 226177ba1f9SLey Foon Tan unsigned int clk_hz; 227177ba1f9SLey Foon Tan 228177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 229177ba1f9SLey Foon Tan switch (main_cfg->mpuclk_src) { 230177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 231177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 232177ba1f9SLey Foon Tan clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) 233177ba1f9SLey Foon Tan + 1; 234177ba1f9SLey Foon Tan break; 235177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 236177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 237177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->mpuclk >> 238177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 239177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 240177ba1f9SLey Foon Tan break; 241177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 242177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 243177ba1f9SLey Foon Tan break; 244177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 245177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 246177ba1f9SLey Foon Tan break; 247177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 248177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 249177ba1f9SLey Foon Tan break; 250177ba1f9SLey Foon Tan default: 251177ba1f9SLey Foon Tan return 0; 252177ba1f9SLey Foon Tan } 253177ba1f9SLey Foon Tan 254177ba1f9SLey Foon Tan clk_hz /= main_cfg->mpuclk_cnt + 1; 255177ba1f9SLey Foon Tan return clk_hz; 256177ba1f9SLey Foon Tan } 257177ba1f9SLey Foon Tan 258177ba1f9SLey Foon Tan /* calculate the intended NOC clock frequency based on handoff */ 259177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, 260177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 261177ba1f9SLey Foon Tan { 262177ba1f9SLey Foon Tan unsigned int clk_hz; 263177ba1f9SLey Foon Tan 264177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 265177ba1f9SLey Foon Tan switch (main_cfg->nocclk_src) { 266177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: 267177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 268177ba1f9SLey Foon Tan clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) 269177ba1f9SLey Foon Tan + 1; 270177ba1f9SLey Foon Tan break; 271177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: 272177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 273177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->nocclk >> 274177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 275177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; 276177ba1f9SLey Foon Tan break; 277177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: 278177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 279177ba1f9SLey Foon Tan break; 280177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: 281177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 282177ba1f9SLey Foon Tan break; 283177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: 284177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 285177ba1f9SLey Foon Tan break; 286177ba1f9SLey Foon Tan default: 287177ba1f9SLey Foon Tan return 0; 288177ba1f9SLey Foon Tan } 289177ba1f9SLey Foon Tan 290177ba1f9SLey Foon Tan clk_hz /= main_cfg->nocclk_cnt + 1; 291177ba1f9SLey Foon Tan return clk_hz; 292177ba1f9SLey Foon Tan } 293177ba1f9SLey Foon Tan 294177ba1f9SLey Foon Tan /* return 1 if PLL ramp is required */ 295177ba1f9SLey Foon Tan static int cm_is_pll_ramp_required(int main0periph1, 296177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 297177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 298177ba1f9SLey Foon Tan { 299177ba1f9SLey Foon Tan /* Check for main PLL */ 300177ba1f9SLey Foon Tan if (main0periph1 == 0) { 301177ba1f9SLey Foon Tan /* 302177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 303177ba1f9SLey Foon Tan * not sourced from main PLL 304177ba1f9SLey Foon Tan */ 305177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 306177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) 307177ba1f9SLey Foon Tan return 0; 308177ba1f9SLey Foon Tan 309177ba1f9SLey Foon Tan /* 310177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock is sourced from main PLL 311177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 312177ba1f9SLey Foon Tan */ 313177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 314177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 315177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 316177ba1f9SLey Foon Tan return 1; 317177ba1f9SLey Foon Tan 318177ba1f9SLey Foon Tan /* 319177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock is sourced from main PLL 320177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 321177ba1f9SLey Foon Tan */ 322177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && 323177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 324177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 325177ba1f9SLey Foon Tan return 2; 326177ba1f9SLey Foon Tan 327177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 328177ba1f9SLey Foon Tan /* 329177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 330177ba1f9SLey Foon Tan * not sourced from periph PLL 331177ba1f9SLey Foon Tan */ 332177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 333177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) 334177ba1f9SLey Foon Tan return 0; 335177ba1f9SLey Foon Tan 336177ba1f9SLey Foon Tan /* 337177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock are source from periph PLL 338177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 339177ba1f9SLey Foon Tan */ 340177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 341177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 342177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 343177ba1f9SLey Foon Tan return 1; 344177ba1f9SLey Foon Tan 345177ba1f9SLey Foon Tan /* 346177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock are source from periph PLL 347177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 348177ba1f9SLey Foon Tan */ 349177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && 350177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 351177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 352177ba1f9SLey Foon Tan return 2; 353177ba1f9SLey Foon Tan } 354177ba1f9SLey Foon Tan 355177ba1f9SLey Foon Tan return 0; 356177ba1f9SLey Foon Tan } 357177ba1f9SLey Foon Tan 358177ba1f9SLey Foon Tan static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, 359177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 360177ba1f9SLey Foon Tan u32 safe_hz, u32 clk_hz) 361177ba1f9SLey Foon Tan { 362177ba1f9SLey Foon Tan u32 cnt; 363177ba1f9SLey Foon Tan u32 clk; 364177ba1f9SLey Foon Tan u32 shift; 365177ba1f9SLey Foon Tan u32 mask; 366177ba1f9SLey Foon Tan u32 denom; 367177ba1f9SLey Foon Tan 368177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 369177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 370177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 371177ba1f9SLey Foon Tan shift = 0; 372177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 373177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 374177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 375177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 376177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 377177ba1f9SLey Foon Tan shift = 0; 378177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 379177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 380177ba1f9SLey Foon Tan } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 381177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 382177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 383177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; 384177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 385177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 386177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 387177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 388177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 389177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; 390177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 391177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 392177ba1f9SLey Foon Tan } else { 393177ba1f9SLey Foon Tan return 0; 394177ba1f9SLey Foon Tan } 395177ba1f9SLey Foon Tan 396177ba1f9SLey Foon Tan return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * 397177ba1f9SLey Foon Tan (1 + denom) - 1; 398177ba1f9SLey Foon Tan } 399177ba1f9SLey Foon Tan 400177ba1f9SLey Foon Tan /* 401177ba1f9SLey Foon Tan * Calculate the new PLL numerator which is based on existing DTS hand off and 402177ba1f9SLey Foon Tan * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the 403177ba1f9SLey Foon Tan * numerator while maintaining denominator as denominator will influence the 404177ba1f9SLey Foon Tan * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final 405177ba1f9SLey Foon Tan * value for numerator is minus with 1 to cater our register value 406177ba1f9SLey Foon Tan * representation. 407177ba1f9SLey Foon Tan */ 408177ba1f9SLey Foon Tan static unsigned int cm_calc_safe_pll_numer(int main0periph1, 409177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 410177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 411177ba1f9SLey Foon Tan unsigned int safe_hz) 412177ba1f9SLey Foon Tan { 413177ba1f9SLey Foon Tan unsigned int clk_hz = 0; 414177ba1f9SLey Foon Tan 415177ba1f9SLey Foon Tan /* Check for main PLL */ 416177ba1f9SLey Foon Tan if (main0periph1 == 0) { 417177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 418177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 419177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 420177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 421177ba1f9SLey Foon Tan break; 422177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 423177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 424177ba1f9SLey Foon Tan break; 425177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 426177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 427177ba1f9SLey Foon Tan break; 428177ba1f9SLey Foon Tan default: 429177ba1f9SLey Foon Tan return 0; 430177ba1f9SLey Foon Tan } 431177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 432177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ 433177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 434177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 435177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 436177ba1f9SLey Foon Tan break; 437177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 438177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 439177ba1f9SLey Foon Tan break; 440177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 441177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 442177ba1f9SLey Foon Tan break; 443177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 444177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 445177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 446177ba1f9SLey Foon Tan break; 447177ba1f9SLey Foon Tan default: 448177ba1f9SLey Foon Tan return 0; 449177ba1f9SLey Foon Tan } 450177ba1f9SLey Foon Tan } else { 451177ba1f9SLey Foon Tan return 0; 452177ba1f9SLey Foon Tan } 453177ba1f9SLey Foon Tan 454177ba1f9SLey Foon Tan return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); 455177ba1f9SLey Foon Tan } 456177ba1f9SLey Foon Tan 457177ba1f9SLey Foon Tan /* ramping the main PLL to final value */ 458177ba1f9SLey Foon Tan static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, 459177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 460177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz) 461177ba1f9SLey Foon Tan { 462177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 463177ba1f9SLey Foon Tan 464177ba1f9SLey Foon Tan /* find out the increment value */ 465177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 466177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 467177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 468177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 469177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 470177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 471177ba1f9SLey Foon Tan } 472177ba1f9SLey Foon Tan 473177ba1f9SLey Foon Tan /* execute the ramping here */ 474177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_main_hz + clk_incr_hz; 475177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 476177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << 477177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 478177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), 479177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 480177ba1f9SLey Foon Tan mdelay(1); 481177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 482177ba1f9SLey Foon Tan } 483177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 484177ba1f9SLey Foon Tan main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); 485177ba1f9SLey Foon Tan mdelay(1); 486177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 487177ba1f9SLey Foon Tan } 488177ba1f9SLey Foon Tan 489177ba1f9SLey Foon Tan /* ramping the periph PLL to final value */ 490177ba1f9SLey Foon Tan static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, 491177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 492177ba1f9SLey Foon Tan unsigned int pll_ramp_periph_hz) 493177ba1f9SLey Foon Tan { 494177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 495177ba1f9SLey Foon Tan 496177ba1f9SLey Foon Tan /* find out the increment value */ 497177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 498177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 499177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 500177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 501177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 502177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 503177ba1f9SLey Foon Tan } 504177ba1f9SLey Foon Tan /* execute the ramping here */ 505177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; 506177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 507177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 508177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), 509177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 510177ba1f9SLey Foon Tan mdelay(1); 511177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 512177ba1f9SLey Foon Tan } 513177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 514177ba1f9SLey Foon Tan per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); 515177ba1f9SLey Foon Tan mdelay(1); 516177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 517177ba1f9SLey Foon Tan } 518177ba1f9SLey Foon Tan 519177ba1f9SLey Foon Tan /* 520177ba1f9SLey Foon Tan * Setup clocks while making no assumptions of the 521177ba1f9SLey Foon Tan * previous state of the clocks. 522177ba1f9SLey Foon Tan * 523177ba1f9SLey Foon Tan * Start by being paranoid and gate all sw managed clocks 524177ba1f9SLey Foon Tan * 525177ba1f9SLey Foon Tan * Put all plls in bypass 526177ba1f9SLey Foon Tan * 527177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value (bgpwr dwn). 528177ba1f9SLey Foon Tan * 529177ba1f9SLey Foon Tan * Put peripheral and main pll src to reset value to avoid glitch. 530177ba1f9SLey Foon Tan * 531177ba1f9SLey Foon Tan * Delay 5 us. 532177ba1f9SLey Foon Tan * 533177ba1f9SLey Foon Tan * Deassert bg pwr dn and set numerator and denominator 534177ba1f9SLey Foon Tan * 535177ba1f9SLey Foon Tan * Start 7 us timer. 536177ba1f9SLey Foon Tan * 537177ba1f9SLey Foon Tan * set internal dividers 538177ba1f9SLey Foon Tan * 539177ba1f9SLey Foon Tan * Wait for 7 us timer. 540177ba1f9SLey Foon Tan * 541177ba1f9SLey Foon Tan * Enable plls 542177ba1f9SLey Foon Tan * 543177ba1f9SLey Foon Tan * Set external dividers while plls are locking 544177ba1f9SLey Foon Tan * 545177ba1f9SLey Foon Tan * Wait for pll lock 546177ba1f9SLey Foon Tan * 547177ba1f9SLey Foon Tan * Assert/deassert outreset all. 548177ba1f9SLey Foon Tan * 549177ba1f9SLey Foon Tan * Take all pll's out of bypass 550177ba1f9SLey Foon Tan * 551177ba1f9SLey Foon Tan * Clear safe mode 552177ba1f9SLey Foon Tan * 553177ba1f9SLey Foon Tan * set source main and peripheral clocks 554177ba1f9SLey Foon Tan * 555177ba1f9SLey Foon Tan * Ungate clocks 556177ba1f9SLey Foon Tan */ 557177ba1f9SLey Foon Tan 558177ba1f9SLey Foon Tan static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 559177ba1f9SLey Foon Tan { 560177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, 561177ba1f9SLey Foon Tan ramp_required; 562177ba1f9SLey Foon Tan 563177ba1f9SLey Foon Tan /* gate off all mainpll clock excpet HW managed clock */ 564177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 565177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 566177ba1f9SLey Foon Tan &clock_manager_base->main_pll.enr); 567177ba1f9SLey Foon Tan 568177ba1f9SLey Foon Tan /* now we can gate off the rest of the peripheral clocks */ 569177ba1f9SLey Foon Tan writel(0, &clock_manager_base->per_pll.en); 570177ba1f9SLey Foon Tan 571177ba1f9SLey Foon Tan /* Put all plls in external bypass */ 572177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 573177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypasss); 574177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 575177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypasss); 576177ba1f9SLey Foon Tan 577177ba1f9SLey Foon Tan /* 578177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value. 579177ba1f9SLey Foon Tan * Some code might have messed with them. At same time set the 580177ba1f9SLey Foon Tan * desired clock source 581177ba1f9SLey Foon Tan */ 582177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO0_RESET | 583177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | 584177ba1f9SLey Foon Tan (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), 585177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 586177ba1f9SLey Foon Tan 587177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO0_RESET | 588177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | 589177ba1f9SLey Foon Tan (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), 590177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 591177ba1f9SLey Foon Tan 592177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); 593177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); 594177ba1f9SLey Foon Tan 595177ba1f9SLey Foon Tan /* clear the interrupt register status register */ 596177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 597177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 598177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 599177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 600177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 601177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | 602177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | 603177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, 604177ba1f9SLey Foon Tan &clock_manager_base->intr); 605177ba1f9SLey Foon Tan 606177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for main PLL */ 607177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); 608177ba1f9SLey Foon Tan if (ramp_required) { 609177ba1f9SLey Foon Tan /* set main PLL to safe starting threshold frequency */ 610177ba1f9SLey Foon Tan if (ramp_required == 1) 611177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 612177ba1f9SLey Foon Tan else if (ramp_required == 2) 613177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 614177ba1f9SLey Foon Tan 615177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 616177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, 617177ba1f9SLey Foon Tan pll_ramp_main_hz), 618177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 619177ba1f9SLey Foon Tan } else 620177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 621177ba1f9SLey Foon Tan main_cfg->vco1_numer, 622177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 623177ba1f9SLey Foon Tan 624177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for periph PLL */ 625177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); 626177ba1f9SLey Foon Tan if (ramp_required) { 627177ba1f9SLey Foon Tan /* set periph PLL to safe starting threshold frequency */ 628177ba1f9SLey Foon Tan if (ramp_required == 1) 629177ba1f9SLey Foon Tan pll_ramp_periph_hz = 630177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 631177ba1f9SLey Foon Tan else if (ramp_required == 2) 632177ba1f9SLey Foon Tan pll_ramp_periph_hz = 633177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 634177ba1f9SLey Foon Tan 635177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 636177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, 637177ba1f9SLey Foon Tan pll_ramp_periph_hz), 638177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 639177ba1f9SLey Foon Tan } else 640177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 641177ba1f9SLey Foon Tan per_cfg->vco1_numer, 642177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 643177ba1f9SLey Foon Tan 644177ba1f9SLey Foon Tan /* Wait for at least 5 us */ 645177ba1f9SLey Foon Tan udelay(5); 646177ba1f9SLey Foon Tan 647177ba1f9SLey Foon Tan /* Now deassert BGPWRDN and PWRDN */ 648177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 649177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | 650177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); 651177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 652177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | 653177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); 654177ba1f9SLey Foon Tan 655177ba1f9SLey Foon Tan /* Wait for at least 7 us */ 656177ba1f9SLey Foon Tan udelay(7); 657177ba1f9SLey Foon Tan 658177ba1f9SLey Foon Tan /* enable the VCO and disable the external regulator to PLL */ 659177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->main_pll.vco0) & 660177ba1f9SLey Foon Tan ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | 661177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_EN_SET_MSK, 662177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 663177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->per_pll.vco0) & 664177ba1f9SLey Foon Tan ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | 665177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_EN_SET_MSK, 666177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 667177ba1f9SLey Foon Tan 668177ba1f9SLey Foon Tan /* setup all the main PLL counter and clock source */ 669177ba1f9SLey Foon Tan writel(main_cfg->nocclk, 670177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); 671177ba1f9SLey Foon Tan writel(main_cfg->mpuclk, 672177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); 673177ba1f9SLey Foon Tan 674177ba1f9SLey Foon Tan /* main_emaca_clk divider */ 675177ba1f9SLey Foon Tan writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); 676177ba1f9SLey Foon Tan /* main_emacb_clk divider */ 677177ba1f9SLey Foon Tan writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); 678177ba1f9SLey Foon Tan /* main_emac_ptp_clk divider */ 679177ba1f9SLey Foon Tan writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); 680177ba1f9SLey Foon Tan /* main_gpio_db_clk divider */ 681177ba1f9SLey Foon Tan writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); 682177ba1f9SLey Foon Tan /* main_sdmmc_clk divider */ 683177ba1f9SLey Foon Tan writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); 684177ba1f9SLey Foon Tan /* main_s2f_user0_clk divider */ 685177ba1f9SLey Foon Tan writel(main_cfg->cntr7clk_cnt | 686177ba1f9SLey Foon Tan (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), 687177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr7clk); 688177ba1f9SLey Foon Tan /* main_s2f_user1_clk divider */ 689177ba1f9SLey Foon Tan writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); 690177ba1f9SLey Foon Tan /* main_hmc_pll_clk divider */ 691177ba1f9SLey Foon Tan writel(main_cfg->cntr9clk_cnt | 692177ba1f9SLey Foon Tan (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), 693177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr9clk); 694177ba1f9SLey Foon Tan /* main_periph_ref_clk divider */ 695177ba1f9SLey Foon Tan writel(main_cfg->cntr15clk_cnt, 696177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr15clk); 697177ba1f9SLey Foon Tan 698177ba1f9SLey Foon Tan /* setup all the peripheral PLL counter and clock source */ 699177ba1f9SLey Foon Tan /* peri_emaca_clk divider */ 700177ba1f9SLey Foon Tan writel(per_cfg->cntr2clk_cnt | 701177ba1f9SLey Foon Tan (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), 702177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr2clk); 703177ba1f9SLey Foon Tan /* peri_emacb_clk divider */ 704177ba1f9SLey Foon Tan writel(per_cfg->cntr3clk_cnt | 705177ba1f9SLey Foon Tan (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), 706177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr3clk); 707177ba1f9SLey Foon Tan /* peri_emac_ptp_clk divider */ 708177ba1f9SLey Foon Tan writel(per_cfg->cntr4clk_cnt | 709177ba1f9SLey Foon Tan (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), 710177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr4clk); 711177ba1f9SLey Foon Tan /* peri_gpio_db_clk divider */ 712177ba1f9SLey Foon Tan writel(per_cfg->cntr5clk_cnt | 713177ba1f9SLey Foon Tan (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), 714177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr5clk); 715177ba1f9SLey Foon Tan /* peri_sdmmc_clk divider */ 716177ba1f9SLey Foon Tan writel(per_cfg->cntr6clk_cnt | 717177ba1f9SLey Foon Tan (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), 718177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr6clk); 719177ba1f9SLey Foon Tan /* peri_s2f_user0_clk divider */ 720177ba1f9SLey Foon Tan writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); 721177ba1f9SLey Foon Tan /* peri_s2f_user1_clk divider */ 722177ba1f9SLey Foon Tan writel(per_cfg->cntr8clk_cnt | 723177ba1f9SLey Foon Tan (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), 724177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr8clk); 725177ba1f9SLey Foon Tan /* peri_hmc_pll_clk divider */ 726177ba1f9SLey Foon Tan writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); 727177ba1f9SLey Foon Tan 728177ba1f9SLey Foon Tan /* setup all the external PLL counter */ 729177ba1f9SLey Foon Tan /* mpu wrapper / external divider */ 730177ba1f9SLey Foon Tan writel(main_cfg->mpuclk_cnt | 731177ba1f9SLey Foon Tan (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), 732177ba1f9SLey Foon Tan &clock_manager_base->main_pll.mpuclk); 733177ba1f9SLey Foon Tan /* NOC wrapper / external divider */ 734177ba1f9SLey Foon Tan writel(main_cfg->nocclk_cnt | 735177ba1f9SLey Foon Tan (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), 736177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocclk); 737177ba1f9SLey Foon Tan /* NOC subclock divider such as l4 */ 738177ba1f9SLey Foon Tan writel(main_cfg->nocdiv_l4mainclk | 739177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4mpclk << 740177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | 741177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4spclk << 742177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | 743177ba1f9SLey Foon Tan (main_cfg->nocdiv_csatclk << 744177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | 745177ba1f9SLey Foon Tan (main_cfg->nocdiv_cstraceclk << 746177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | 747177ba1f9SLey Foon Tan (main_cfg->nocdiv_cspdbclk << 748177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), 749177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocdiv); 750177ba1f9SLey Foon Tan /* gpio_db external divider */ 751177ba1f9SLey Foon Tan writel(per_cfg->gpiodiv_gpiodbclk, 752177ba1f9SLey Foon Tan &clock_manager_base->per_pll.gpiodiv); 753177ba1f9SLey Foon Tan 754177ba1f9SLey Foon Tan /* setup the EMAC clock mux select */ 755177ba1f9SLey Foon Tan writel((per_cfg->emacctl_emac0sel << 756177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | 757177ba1f9SLey Foon Tan (per_cfg->emacctl_emac1sel << 758177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | 759177ba1f9SLey Foon Tan (per_cfg->emacctl_emac2sel << 760177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), 761177ba1f9SLey Foon Tan &clock_manager_base->per_pll.emacctl); 762177ba1f9SLey Foon Tan 763177ba1f9SLey Foon Tan /* at this stage, check for PLL lock status */ 764177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 765177ba1f9SLey Foon Tan 766177ba1f9SLey Foon Tan /* 767177ba1f9SLey Foon Tan * after locking, but before taking out of bypass, 768177ba1f9SLey Foon Tan * assert/deassert outresetall 769177ba1f9SLey Foon Tan */ 770177ba1f9SLey Foon Tan /* assert mainpll outresetall */ 771177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->main_pll.vco0, 772177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 773177ba1f9SLey Foon Tan /* assert perpll outresetall */ 774177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->per_pll.vco0, 775177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 776177ba1f9SLey Foon Tan /* de-assert mainpll outresetall */ 777177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 778177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 779177ba1f9SLey Foon Tan /* de-assert perpll outresetall */ 780177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 781177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 782177ba1f9SLey Foon Tan 783177ba1f9SLey Foon Tan /* Take all PLLs out of bypass when boot mode is cleared. */ 784177ba1f9SLey Foon Tan /* release mainpll from bypass */ 785177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 786177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypassr); 787177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 788177ba1f9SLey Foon Tan cm_wait_for_fsm(); 789177ba1f9SLey Foon Tan 790177ba1f9SLey Foon Tan /* release perpll from bypass */ 791177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 792177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypassr); 793177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 794177ba1f9SLey Foon Tan cm_wait_for_fsm(); 795177ba1f9SLey Foon Tan 796177ba1f9SLey Foon Tan /* clear boot mode */ 797177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->ctrl, 798177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); 799177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 800177ba1f9SLey Foon Tan cm_wait_for_fsm(); 801177ba1f9SLey Foon Tan 802177ba1f9SLey Foon Tan /* At here, we need to ramp to final value if needed */ 803177ba1f9SLey Foon Tan if (pll_ramp_main_hz != 0) 804177ba1f9SLey Foon Tan cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); 805177ba1f9SLey Foon Tan if (pll_ramp_periph_hz != 0) 806177ba1f9SLey Foon Tan cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); 807177ba1f9SLey Foon Tan 808177ba1f9SLey Foon Tan /* Now ungate non-hw-managed clocks */ 809177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 810177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 811177ba1f9SLey Foon Tan &clock_manager_base->main_pll.ens); 812177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); 813177ba1f9SLey Foon Tan 814177ba1f9SLey Foon Tan /* Clear the loss lock and slip bits as they might set during 815177ba1f9SLey Foon Tan clock reconfiguration */ 816177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 817177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 818177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 819177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 820177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 821177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, 822177ba1f9SLey Foon Tan &clock_manager_base->intr); 823177ba1f9SLey Foon Tan 824177ba1f9SLey Foon Tan return 0; 825177ba1f9SLey Foon Tan } 826177ba1f9SLey Foon Tan 827177ba1f9SLey Foon Tan void cm_use_intosc(void) 828177ba1f9SLey Foon Tan { 829177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->ctrl, 830177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); 831177ba1f9SLey Foon Tan } 832177ba1f9SLey Foon Tan 833177ba1f9SLey Foon Tan unsigned int cm_get_noc_clk_hz(void) 834177ba1f9SLey Foon Tan { 835177ba1f9SLey Foon Tan unsigned int clk_src, divisor, nocclk, src_hz; 836177ba1f9SLey Foon Tan 837177ba1f9SLey Foon Tan nocclk = readl(&clock_manager_base->main_pll.nocclk); 838177ba1f9SLey Foon Tan clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & 839177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_SRC_MSK; 840177ba1f9SLey Foon Tan 841177ba1f9SLey Foon Tan divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK); 842177ba1f9SLey Foon Tan 843177ba1f9SLey Foon Tan if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { 844177ba1f9SLey Foon Tan src_hz = cm_get_main_vco_clk_hz(); 845177ba1f9SLey Foon Tan src_hz /= 1 + 846177ba1f9SLey Foon Tan (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) & 847177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 848177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { 849177ba1f9SLey Foon Tan src_hz = cm_get_per_vco_clk_hz(); 850177ba1f9SLey Foon Tan src_hz /= 1 + 851177ba1f9SLey Foon Tan ((readl(SOCFPGA_CLKMGR_ADDRESS + 852177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOC_CLK_OFFSET) >> 853177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 854177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 855177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { 856177ba1f9SLey Foon Tan src_hz = eosc1_hz; 857177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { 858177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 859177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { 860177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 861177ba1f9SLey Foon Tan } else { 862177ba1f9SLey Foon Tan src_hz = 0; 863177ba1f9SLey Foon Tan } 864177ba1f9SLey Foon Tan 865177ba1f9SLey Foon Tan return src_hz / divisor; 866177ba1f9SLey Foon Tan } 867177ba1f9SLey Foon Tan 868177ba1f9SLey Foon Tan unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift) 869177ba1f9SLey Foon Tan { 870177ba1f9SLey Foon Tan unsigned int divisor2 = 1 << 871177ba1f9SLey Foon Tan ((readl(&clock_manager_base->main_pll.nocdiv) >> 872177ba1f9SLey Foon Tan nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK); 873177ba1f9SLey Foon Tan 874177ba1f9SLey Foon Tan return cm_get_noc_clk_hz() / divisor2; 875177ba1f9SLey Foon Tan } 876177ba1f9SLey Foon Tan 877177ba1f9SLey Foon Tan int cm_basic_init(const void *blob) 878177ba1f9SLey Foon Tan { 879177ba1f9SLey Foon Tan struct mainpll_cfg main_cfg; 880177ba1f9SLey Foon Tan struct perpll_cfg per_cfg; 881177ba1f9SLey Foon Tan struct alteragrp_cfg altrgrp_cfg; 882177ba1f9SLey Foon Tan int rval; 883177ba1f9SLey Foon Tan 884177ba1f9SLey Foon Tan /* initialize to zero for use case of optional node */ 885177ba1f9SLey Foon Tan memset(&main_cfg, 0, sizeof(main_cfg)); 886177ba1f9SLey Foon Tan memset(&per_cfg, 0, sizeof(per_cfg)); 887177ba1f9SLey Foon Tan memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg)); 888177ba1f9SLey Foon Tan 889177ba1f9SLey Foon Tan rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg); 890177ba1f9SLey Foon Tan if (rval) 891177ba1f9SLey Foon Tan return rval; 892177ba1f9SLey Foon Tan 893177ba1f9SLey Foon Tan rval = cm_full_cfg(&main_cfg, &per_cfg); 894177ba1f9SLey Foon Tan 895177ba1f9SLey Foon Tan cm_l4_main_clk_hz = 896177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 897177ba1f9SLey Foon Tan 898177ba1f9SLey Foon Tan cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 899177ba1f9SLey Foon Tan 900177ba1f9SLey Foon Tan cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz(); 901177ba1f9SLey Foon Tan 902177ba1f9SLey Foon Tan cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4; 903177ba1f9SLey Foon Tan 904177ba1f9SLey Foon Tan return rval; 905177ba1f9SLey Foon Tan } 906177ba1f9SLey Foon Tan 907177ba1f9SLey Foon Tan unsigned long cm_get_mpu_clk_hz(void) 908177ba1f9SLey Foon Tan { 909177ba1f9SLey Foon Tan u32 reg, clk_hz; 910177ba1f9SLey Foon Tan u32 clk_src, mainmpuclk_reg; 911177ba1f9SLey Foon Tan 912177ba1f9SLey Foon Tan mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); 913177ba1f9SLey Foon Tan 914177ba1f9SLey Foon Tan clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & 915177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_SRC_MSK; 916177ba1f9SLey Foon Tan 917177ba1f9SLey Foon Tan reg = readl(&clock_manager_base->altera.mpuclk); 918177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 919177ba1f9SLey Foon Tan switch (clk_src) { 920177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 921177ba1f9SLey Foon Tan clk_hz = cm_get_main_vco_clk_hz(); 922177ba1f9SLey Foon Tan clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 923177ba1f9SLey Foon Tan break; 924177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 925177ba1f9SLey Foon Tan clk_hz = cm_get_per_vco_clk_hz(); 926177ba1f9SLey Foon Tan clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 927177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); 928177ba1f9SLey Foon Tan break; 929177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 930177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 931177ba1f9SLey Foon Tan break; 932177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 933177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 934177ba1f9SLey Foon Tan break; 935177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 936177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 937177ba1f9SLey Foon Tan break; 938177ba1f9SLey Foon Tan default: 939177ba1f9SLey Foon Tan printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src); 940177ba1f9SLey Foon Tan return 0; 941177ba1f9SLey Foon Tan } 942177ba1f9SLey Foon Tan 943177ba1f9SLey Foon Tan clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 944177ba1f9SLey Foon Tan 945177ba1f9SLey Foon Tan return clk_hz; 946177ba1f9SLey Foon Tan } 947177ba1f9SLey Foon Tan 948177ba1f9SLey Foon Tan unsigned int cm_get_per_vco_clk_hz(void) 949177ba1f9SLey Foon Tan { 950177ba1f9SLey Foon Tan u32 src_hz = 0; 951177ba1f9SLey Foon Tan u32 clk_src = 0; 952177ba1f9SLey Foon Tan u32 numer = 0; 953177ba1f9SLey Foon Tan u32 denom = 0; 954177ba1f9SLey Foon Tan u32 vco = 0; 955177ba1f9SLey Foon Tan 956177ba1f9SLey Foon Tan clk_src = readl(&clock_manager_base->per_pll.vco0); 957177ba1f9SLey Foon Tan 958177ba1f9SLey Foon Tan clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) & 959177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PSRC_MSK; 960177ba1f9SLey Foon Tan 961177ba1f9SLey Foon Tan if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) { 962177ba1f9SLey Foon Tan src_hz = eosc1_hz; 963177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) { 964177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 965177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) { 966177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 967177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) { 968177ba1f9SLey Foon Tan src_hz = cm_get_main_vco_clk_hz(); 969177ba1f9SLey Foon Tan src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) & 970177ba1f9SLey Foon Tan CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; 971177ba1f9SLey Foon Tan } else { 972177ba1f9SLey Foon Tan printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src); 973177ba1f9SLey Foon Tan return 0; 974177ba1f9SLey Foon Tan } 975177ba1f9SLey Foon Tan 976177ba1f9SLey Foon Tan vco = readl(&clock_manager_base->per_pll.vco1); 977177ba1f9SLey Foon Tan 978177ba1f9SLey Foon Tan numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; 979177ba1f9SLey Foon Tan 980177ba1f9SLey Foon Tan denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & 981177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO1_DENOM_MSK; 982177ba1f9SLey Foon Tan 983177ba1f9SLey Foon Tan vco = src_hz; 984177ba1f9SLey Foon Tan vco /= 1 + denom; 985177ba1f9SLey Foon Tan vco *= 1 + numer; 986177ba1f9SLey Foon Tan 987177ba1f9SLey Foon Tan return vco; 988177ba1f9SLey Foon Tan } 989177ba1f9SLey Foon Tan 990177ba1f9SLey Foon Tan unsigned int cm_get_main_vco_clk_hz(void) 991177ba1f9SLey Foon Tan { 992177ba1f9SLey Foon Tan u32 src_hz, numer, denom, vco; 993177ba1f9SLey Foon Tan 994177ba1f9SLey Foon Tan u32 clk_src = readl(&clock_manager_base->main_pll.vco0); 995177ba1f9SLey Foon Tan 996177ba1f9SLey Foon Tan clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) & 997177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PSRC_MSK; 998177ba1f9SLey Foon Tan 999177ba1f9SLey Foon Tan if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) { 1000177ba1f9SLey Foon Tan src_hz = eosc1_hz; 1001177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) { 1002177ba1f9SLey Foon Tan src_hz = cb_intosc_hz; 1003177ba1f9SLey Foon Tan } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) { 1004177ba1f9SLey Foon Tan src_hz = f2s_free_hz; 1005177ba1f9SLey Foon Tan } else { 1006177ba1f9SLey Foon Tan printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src); 1007177ba1f9SLey Foon Tan return 0; 1008177ba1f9SLey Foon Tan } 1009177ba1f9SLey Foon Tan 1010177ba1f9SLey Foon Tan vco = readl(&clock_manager_base->main_pll.vco1); 1011177ba1f9SLey Foon Tan 1012177ba1f9SLey Foon Tan numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK; 1013177ba1f9SLey Foon Tan 1014177ba1f9SLey Foon Tan denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & 1015177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_MSK; 1016177ba1f9SLey Foon Tan 1017177ba1f9SLey Foon Tan vco = src_hz; 1018177ba1f9SLey Foon Tan vco /= 1 + denom; 1019177ba1f9SLey Foon Tan vco *= 1 + numer; 1020177ba1f9SLey Foon Tan 1021177ba1f9SLey Foon Tan return vco; 1022177ba1f9SLey Foon Tan } 1023177ba1f9SLey Foon Tan 1024177ba1f9SLey Foon Tan unsigned int cm_get_l4_sp_clk_hz(void) 1025177ba1f9SLey Foon Tan { 1026177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB); 1027177ba1f9SLey Foon Tan } 1028177ba1f9SLey Foon Tan 1029177ba1f9SLey Foon Tan unsigned int cm_get_mmc_controller_clk_hz(void) 1030177ba1f9SLey Foon Tan { 1031177ba1f9SLey Foon Tan u32 clk_hz = 0; 1032177ba1f9SLey Foon Tan u32 clk_input = 0; 1033177ba1f9SLey Foon Tan 1034177ba1f9SLey Foon Tan clk_input = readl(&clock_manager_base->per_pll.cntr6clk); 1035177ba1f9SLey Foon Tan clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & 1036177ba1f9SLey Foon Tan CLKMGR_PERPLLGRP_SRC_MSK; 1037177ba1f9SLey Foon Tan 1038177ba1f9SLey Foon Tan switch (clk_input) { 1039177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_MAIN: 1040177ba1f9SLey Foon Tan clk_hz = cm_get_main_vco_clk_hz(); 1041177ba1f9SLey Foon Tan clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & 1042177ba1f9SLey Foon Tan CLKMGR_MAINPLL_CNTRCLK_MSK); 1043177ba1f9SLey Foon Tan break; 1044177ba1f9SLey Foon Tan 1045177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_PERI: 1046177ba1f9SLey Foon Tan clk_hz = cm_get_per_vco_clk_hz(); 1047177ba1f9SLey Foon Tan clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & 1048177ba1f9SLey Foon Tan CLKMGR_PERPLL_CNTRCLK_MSK); 1049177ba1f9SLey Foon Tan break; 1050177ba1f9SLey Foon Tan 1051177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_OSC1: 1052177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 1053177ba1f9SLey Foon Tan break; 1054177ba1f9SLey Foon Tan 1055177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_INTOSC: 1056177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 1057177ba1f9SLey Foon Tan break; 1058177ba1f9SLey Foon Tan 1059177ba1f9SLey Foon Tan case CLKMGR_PERPLLGRP_SRC_FPGA: 1060177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 1061177ba1f9SLey Foon Tan break; 1062177ba1f9SLey Foon Tan } 1063177ba1f9SLey Foon Tan 1064177ba1f9SLey Foon Tan return clk_hz / 4; 1065177ba1f9SLey Foon Tan } 1066177ba1f9SLey Foon Tan 1067177ba1f9SLey Foon Tan unsigned int cm_get_spi_controller_clk_hz(void) 1068177ba1f9SLey Foon Tan { 1069177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 1070177ba1f9SLey Foon Tan } 1071177ba1f9SLey Foon Tan 1072177ba1f9SLey Foon Tan unsigned int cm_get_qspi_controller_clk_hz(void) 1073177ba1f9SLey Foon Tan { 1074177ba1f9SLey Foon Tan return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 1075177ba1f9SLey Foon Tan } 1076177ba1f9SLey Foon Tan 107721143ce1SEugeniy Paltsev /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ 107821143ce1SEugeniy Paltsev int dw_spi_get_clk(struct udevice *bus, ulong *rate) 107921143ce1SEugeniy Paltsev { 108021143ce1SEugeniy Paltsev *rate = cm_get_spi_controller_clk_hz(); 108121143ce1SEugeniy Paltsev 108221143ce1SEugeniy Paltsev return 0; 108321143ce1SEugeniy Paltsev } 108421143ce1SEugeniy Paltsev 1085177ba1f9SLey Foon Tan void cm_print_clock_quick_summary(void) 1086177ba1f9SLey Foon Tan { 1087177ba1f9SLey Foon Tan printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); 1088177ba1f9SLey Foon Tan printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); 1089177ba1f9SLey Foon Tan printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); 1090177ba1f9SLey Foon Tan printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); 1091177ba1f9SLey Foon Tan printf("EOSC1 %8d kHz\n", eosc1_hz / 1000); 1092177ba1f9SLey Foon Tan printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000); 1093177ba1f9SLey Foon Tan printf("f2s_free %8d kHz\n", f2s_free_hz / 1000); 1094177ba1f9SLey Foon Tan printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000); 1095177ba1f9SLey Foon Tan printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000); 1096177ba1f9SLey Foon Tan printf("L4 Main %8d kHz\n", 1097177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000); 1098177ba1f9SLey Foon Tan printf("L4 MP %8d kHz\n", 1099177ba1f9SLey Foon Tan cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000); 1100177ba1f9SLey Foon Tan printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); 1101177ba1f9SLey Foon Tan printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000); 1102177ba1f9SLey Foon Tan } 1103