183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2177ba1f9SLey Foon Tan /* 3177ba1f9SLey Foon Tan * Copyright (C) 2016-2017 Intel Corporation 4177ba1f9SLey Foon Tan */ 5177ba1f9SLey Foon Tan 6177ba1f9SLey Foon Tan #include <common.h> 7177ba1f9SLey Foon Tan #include <fdtdec.h> 8177ba1f9SLey Foon Tan #include <asm/io.h> 921143ce1SEugeniy Paltsev #include <dm.h> 10934aec71SMarek Vasut #include <clk.h> 11934aec71SMarek Vasut #include <dm/device-internal.h> 12177ba1f9SLey Foon Tan #include <asm/arch/clock_manager.h> 13177ba1f9SLey Foon Tan 14*0b8f6378SMarek Vasut #ifdef CONFIG_SPL_BUILD 15480f7f9cSMarek Vasut 16177ba1f9SLey Foon Tan static u32 eosc1_hz; 17177ba1f9SLey Foon Tan static u32 cb_intosc_hz; 18177ba1f9SLey Foon Tan static u32 f2s_free_hz; 19177ba1f9SLey Foon Tan 20177ba1f9SLey Foon Tan struct mainpll_cfg { 21177ba1f9SLey Foon Tan u32 vco0_psrc; 22177ba1f9SLey Foon Tan u32 vco1_denom; 23177ba1f9SLey Foon Tan u32 vco1_numer; 24177ba1f9SLey Foon Tan u32 mpuclk; 25177ba1f9SLey Foon Tan u32 mpuclk_cnt; 26177ba1f9SLey Foon Tan u32 mpuclk_src; 27177ba1f9SLey Foon Tan u32 nocclk; 28177ba1f9SLey Foon Tan u32 nocclk_cnt; 29177ba1f9SLey Foon Tan u32 nocclk_src; 30177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 31177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 32177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 33177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 34177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 35177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 36177ba1f9SLey Foon Tan u32 cntr7clk_src; 37177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 38177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 39177ba1f9SLey Foon Tan u32 cntr9clk_src; 40177ba1f9SLey Foon Tan u32 cntr15clk_cnt; 41177ba1f9SLey Foon Tan u32 nocdiv_l4mainclk; 42177ba1f9SLey Foon Tan u32 nocdiv_l4mpclk; 43177ba1f9SLey Foon Tan u32 nocdiv_l4spclk; 44177ba1f9SLey Foon Tan u32 nocdiv_csatclk; 45177ba1f9SLey Foon Tan u32 nocdiv_cstraceclk; 46177ba1f9SLey Foon Tan u32 nocdiv_cspdbclk; 47177ba1f9SLey Foon Tan }; 48177ba1f9SLey Foon Tan 49177ba1f9SLey Foon Tan struct perpll_cfg { 50177ba1f9SLey Foon Tan u32 vco0_psrc; 51177ba1f9SLey Foon Tan u32 vco1_denom; 52177ba1f9SLey Foon Tan u32 vco1_numer; 53177ba1f9SLey Foon Tan u32 cntr2clk_cnt; 54177ba1f9SLey Foon Tan u32 cntr2clk_src; 55177ba1f9SLey Foon Tan u32 cntr3clk_cnt; 56177ba1f9SLey Foon Tan u32 cntr3clk_src; 57177ba1f9SLey Foon Tan u32 cntr4clk_cnt; 58177ba1f9SLey Foon Tan u32 cntr4clk_src; 59177ba1f9SLey Foon Tan u32 cntr5clk_cnt; 60177ba1f9SLey Foon Tan u32 cntr5clk_src; 61177ba1f9SLey Foon Tan u32 cntr6clk_cnt; 62177ba1f9SLey Foon Tan u32 cntr6clk_src; 63177ba1f9SLey Foon Tan u32 cntr7clk_cnt; 64177ba1f9SLey Foon Tan u32 cntr8clk_cnt; 65177ba1f9SLey Foon Tan u32 cntr8clk_src; 66177ba1f9SLey Foon Tan u32 cntr9clk_cnt; 67480f7f9cSMarek Vasut u32 cntr9clk_src; 68177ba1f9SLey Foon Tan u32 emacctl_emac0sel; 69177ba1f9SLey Foon Tan u32 emacctl_emac1sel; 70177ba1f9SLey Foon Tan u32 emacctl_emac2sel; 71177ba1f9SLey Foon Tan u32 gpiodiv_gpiodbclk; 72177ba1f9SLey Foon Tan }; 73177ba1f9SLey Foon Tan 74480f7f9cSMarek Vasut struct strtou32 { 75480f7f9cSMarek Vasut const char *str; 76480f7f9cSMarek Vasut const u32 val; 77177ba1f9SLey Foon Tan }; 78177ba1f9SLey Foon Tan 79480f7f9cSMarek Vasut static const struct strtou32 mainpll_cfg_tab[] = { 80480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, 81480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, 82480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, 83480f7f9cSMarek Vasut { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, 84480f7f9cSMarek Vasut { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, 85480f7f9cSMarek Vasut { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, 86480f7f9cSMarek Vasut { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) }, 87480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) }, 88480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) }, 89480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) }, 90480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) }, 91480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) }, 92480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) }, 93480f7f9cSMarek Vasut { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) }, 94480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) }, 95480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) }, 96480f7f9cSMarek Vasut { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) }, 97480f7f9cSMarek Vasut { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) }, 98480f7f9cSMarek Vasut { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) }, 99480f7f9cSMarek Vasut { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) }, 100480f7f9cSMarek Vasut { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) }, 101480f7f9cSMarek Vasut { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) }, 102480f7f9cSMarek Vasut { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) }, 103480f7f9cSMarek Vasut { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) }, 104480f7f9cSMarek Vasut }; 105177ba1f9SLey Foon Tan 106480f7f9cSMarek Vasut static const struct strtou32 perpll_cfg_tab[] = { 107480f7f9cSMarek Vasut { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) }, 108480f7f9cSMarek Vasut { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) }, 109480f7f9cSMarek Vasut { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) }, 110480f7f9cSMarek Vasut { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) }, 111480f7f9cSMarek Vasut { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) }, 112480f7f9cSMarek Vasut { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) }, 113480f7f9cSMarek Vasut { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) }, 114480f7f9cSMarek Vasut { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) }, 115480f7f9cSMarek Vasut { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) }, 116480f7f9cSMarek Vasut { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) }, 117480f7f9cSMarek Vasut { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) }, 118480f7f9cSMarek Vasut { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) }, 119480f7f9cSMarek Vasut { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) }, 120480f7f9cSMarek Vasut { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) }, 121480f7f9cSMarek Vasut { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) }, 122480f7f9cSMarek Vasut { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) }, 123480f7f9cSMarek Vasut { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) }, 124480f7f9cSMarek Vasut { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) }, 125480f7f9cSMarek Vasut { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) }, 126480f7f9cSMarek Vasut { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) }, 127480f7f9cSMarek Vasut { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) }, 128480f7f9cSMarek Vasut }; 129480f7f9cSMarek Vasut 130480f7f9cSMarek Vasut static const struct strtou32 alteragrp_cfg_tab[] = { 131480f7f9cSMarek Vasut { "nocclk", offsetof(struct mainpll_cfg, nocclk) }, 132480f7f9cSMarek Vasut { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) }, 133480f7f9cSMarek Vasut }; 134480f7f9cSMarek Vasut 135480f7f9cSMarek Vasut struct strtopu32 { 136480f7f9cSMarek Vasut const char *str; 137480f7f9cSMarek Vasut u32 *p; 138480f7f9cSMarek Vasut }; 139480f7f9cSMarek Vasut 140480f7f9cSMarek Vasut const struct strtopu32 dt_to_val[] = { 141934aec71SMarek Vasut { "altera_arria10_hps_eosc1", &eosc1_hz }, 142934aec71SMarek Vasut { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, 143934aec71SMarek Vasut { "altera_arria10_hps_f2h_free", &f2s_free_hz }, 144480f7f9cSMarek Vasut }; 145480f7f9cSMarek Vasut 146480f7f9cSMarek Vasut static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, 147480f7f9cSMarek Vasut int cfg_tab_len, void *cfg) 148177ba1f9SLey Foon Tan { 149480f7f9cSMarek Vasut int i; 150480f7f9cSMarek Vasut u32 val; 151480f7f9cSMarek Vasut 152480f7f9cSMarek Vasut for (i = 0; i < cfg_tab_len; i++) { 153480f7f9cSMarek Vasut if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) { 154177ba1f9SLey Foon Tan /* could not find required property */ 155177ba1f9SLey Foon Tan return -EINVAL; 156177ba1f9SLey Foon Tan } 157480f7f9cSMarek Vasut *(u32 *)(cfg + cfg_tab[i].val) = val; 158480f7f9cSMarek Vasut } 159177ba1f9SLey Foon Tan 160177ba1f9SLey Foon Tan return 0; 161177ba1f9SLey Foon Tan } 162177ba1f9SLey Foon Tan 163934aec71SMarek Vasut static int of_get_input_clks(const void *blob) 164177ba1f9SLey Foon Tan { 165934aec71SMarek Vasut struct udevice *dev; 166934aec71SMarek Vasut struct clk clk; 167934aec71SMarek Vasut int i, ret; 168177ba1f9SLey Foon Tan 169480f7f9cSMarek Vasut for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { 170934aec71SMarek Vasut memset(&clk, 0, sizeof(clk)); 171480f7f9cSMarek Vasut 172934aec71SMarek Vasut ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, 173934aec71SMarek Vasut &dev); 174934aec71SMarek Vasut if (ret) 175934aec71SMarek Vasut return ret; 176480f7f9cSMarek Vasut 177934aec71SMarek Vasut ret = clk_request(dev, &clk); 178934aec71SMarek Vasut if (ret) 179934aec71SMarek Vasut return ret; 180934aec71SMarek Vasut 181934aec71SMarek Vasut *dt_to_val[i].p = clk_get_rate(&clk); 182480f7f9cSMarek Vasut } 183934aec71SMarek Vasut 184934aec71SMarek Vasut return 0; 185177ba1f9SLey Foon Tan } 186177ba1f9SLey Foon Tan 187177ba1f9SLey Foon Tan static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, 188480f7f9cSMarek Vasut struct perpll_cfg *per_cfg) 189177ba1f9SLey Foon Tan { 190934aec71SMarek Vasut int ret, node, child, len; 191177ba1f9SLey Foon Tan const char *node_name; 192177ba1f9SLey Foon Tan 193934aec71SMarek Vasut ret = of_get_input_clks(blob); 194934aec71SMarek Vasut if (ret) 195934aec71SMarek Vasut return ret; 196480f7f9cSMarek Vasut 197480f7f9cSMarek Vasut node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); 198480f7f9cSMarek Vasut 199177ba1f9SLey Foon Tan if (node < 0) 200177ba1f9SLey Foon Tan return -EINVAL; 201177ba1f9SLey Foon Tan 202177ba1f9SLey Foon Tan child = fdt_first_subnode(blob, node); 203177ba1f9SLey Foon Tan 204177ba1f9SLey Foon Tan if (child < 0) 205177ba1f9SLey Foon Tan return -EINVAL; 206177ba1f9SLey Foon Tan 207177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 208177ba1f9SLey Foon Tan 209177ba1f9SLey Foon Tan while (node_name) { 210480f7f9cSMarek Vasut if (!strcmp(node_name, "mainpll")) { 211480f7f9cSMarek Vasut if (of_to_struct(blob, child, mainpll_cfg_tab, 212480f7f9cSMarek Vasut ARRAY_SIZE(mainpll_cfg_tab), main_cfg)) 213177ba1f9SLey Foon Tan return -EINVAL; 214480f7f9cSMarek Vasut } else if (!strcmp(node_name, "perpll")) { 215480f7f9cSMarek Vasut if (of_to_struct(blob, child, perpll_cfg_tab, 216480f7f9cSMarek Vasut ARRAY_SIZE(perpll_cfg_tab), per_cfg)) 217177ba1f9SLey Foon Tan return -EINVAL; 218480f7f9cSMarek Vasut } else if (!strcmp(node_name, "alteragrp")) { 219480f7f9cSMarek Vasut if (of_to_struct(blob, child, alteragrp_cfg_tab, 220480f7f9cSMarek Vasut ARRAY_SIZE(alteragrp_cfg_tab), main_cfg)) 221177ba1f9SLey Foon Tan return -EINVAL; 222177ba1f9SLey Foon Tan } 223177ba1f9SLey Foon Tan child = fdt_next_subnode(blob, child); 224177ba1f9SLey Foon Tan 225177ba1f9SLey Foon Tan if (child < 0) 226177ba1f9SLey Foon Tan break; 227177ba1f9SLey Foon Tan 228177ba1f9SLey Foon Tan node_name = fdt_get_name(blob, child, &len); 229177ba1f9SLey Foon Tan } 230177ba1f9SLey Foon Tan 231177ba1f9SLey Foon Tan return 0; 232177ba1f9SLey Foon Tan } 233177ba1f9SLey Foon Tan 234*0b8f6378SMarek Vasut static const struct socfpga_clock_manager *clock_manager_base = 235*0b8f6378SMarek Vasut (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 236*0b8f6378SMarek Vasut 237177ba1f9SLey Foon Tan /* calculate the intended main VCO frequency based on handoff */ 238177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_main_vco_clk_hz 239177ba1f9SLey Foon Tan (struct mainpll_cfg *main_cfg) 240177ba1f9SLey Foon Tan { 241177ba1f9SLey Foon Tan unsigned int clk_hz; 242177ba1f9SLey Foon Tan 243177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 244177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 245177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 246177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 247177ba1f9SLey Foon Tan break; 248177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 249177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 250177ba1f9SLey Foon Tan break; 251177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 252177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 253177ba1f9SLey Foon Tan break; 254177ba1f9SLey Foon Tan default: 255177ba1f9SLey Foon Tan return 0; 256177ba1f9SLey Foon Tan } 257177ba1f9SLey Foon Tan 258177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 259177ba1f9SLey Foon Tan clk_hz /= 1 + main_cfg->vco1_denom; 260177ba1f9SLey Foon Tan clk_hz *= 1 + main_cfg->vco1_numer; 261177ba1f9SLey Foon Tan 262177ba1f9SLey Foon Tan return clk_hz; 263177ba1f9SLey Foon Tan } 264177ba1f9SLey Foon Tan 265177ba1f9SLey Foon Tan /* calculate the intended periph VCO frequency based on handoff */ 266177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_periph_vco_clk_hz( 267177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 268177ba1f9SLey Foon Tan { 269177ba1f9SLey Foon Tan unsigned int clk_hz; 270177ba1f9SLey Foon Tan 271177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ 272177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 273177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 274177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 275177ba1f9SLey Foon Tan break; 276177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 277177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 278177ba1f9SLey Foon Tan break; 279177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 280177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 281177ba1f9SLey Foon Tan break; 282177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 283177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 284177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 285177ba1f9SLey Foon Tan break; 286177ba1f9SLey Foon Tan default: 287177ba1f9SLey Foon Tan return 0; 288177ba1f9SLey Foon Tan } 289177ba1f9SLey Foon Tan 290177ba1f9SLey Foon Tan /* calculate the VCO frequency */ 291177ba1f9SLey Foon Tan clk_hz /= 1 + per_cfg->vco1_denom; 292177ba1f9SLey Foon Tan clk_hz *= 1 + per_cfg->vco1_numer; 293177ba1f9SLey Foon Tan 294177ba1f9SLey Foon Tan return clk_hz; 295177ba1f9SLey Foon Tan } 296177ba1f9SLey Foon Tan 297177ba1f9SLey Foon Tan /* calculate the intended MPU clock frequency based on handoff */ 298177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, 299177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 300177ba1f9SLey Foon Tan { 301177ba1f9SLey Foon Tan unsigned int clk_hz; 302177ba1f9SLey Foon Tan 303177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 304177ba1f9SLey Foon Tan switch (main_cfg->mpuclk_src) { 305177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 306177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 307177ba1f9SLey Foon Tan clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) 308177ba1f9SLey Foon Tan + 1; 309177ba1f9SLey Foon Tan break; 310177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 311177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 312177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->mpuclk >> 313177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 314177ba1f9SLey Foon Tan CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 315177ba1f9SLey Foon Tan break; 316177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 317177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 318177ba1f9SLey Foon Tan break; 319177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 320177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 321177ba1f9SLey Foon Tan break; 322177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 323177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 324177ba1f9SLey Foon Tan break; 325177ba1f9SLey Foon Tan default: 326177ba1f9SLey Foon Tan return 0; 327177ba1f9SLey Foon Tan } 328177ba1f9SLey Foon Tan 329177ba1f9SLey Foon Tan clk_hz /= main_cfg->mpuclk_cnt + 1; 330177ba1f9SLey Foon Tan return clk_hz; 331177ba1f9SLey Foon Tan } 332177ba1f9SLey Foon Tan 333177ba1f9SLey Foon Tan /* calculate the intended NOC clock frequency based on handoff */ 334177ba1f9SLey Foon Tan static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, 335177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 336177ba1f9SLey Foon Tan { 337177ba1f9SLey Foon Tan unsigned int clk_hz; 338177ba1f9SLey Foon Tan 339177ba1f9SLey Foon Tan /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 340177ba1f9SLey Foon Tan switch (main_cfg->nocclk_src) { 341177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: 342177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 343177ba1f9SLey Foon Tan clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) 344177ba1f9SLey Foon Tan + 1; 345177ba1f9SLey Foon Tan break; 346177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: 347177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 348177ba1f9SLey Foon Tan clk_hz /= ((main_cfg->nocclk >> 349177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 350177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; 351177ba1f9SLey Foon Tan break; 352177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: 353177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 354177ba1f9SLey Foon Tan break; 355177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: 356177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 357177ba1f9SLey Foon Tan break; 358177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: 359177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 360177ba1f9SLey Foon Tan break; 361177ba1f9SLey Foon Tan default: 362177ba1f9SLey Foon Tan return 0; 363177ba1f9SLey Foon Tan } 364177ba1f9SLey Foon Tan 365177ba1f9SLey Foon Tan clk_hz /= main_cfg->nocclk_cnt + 1; 366177ba1f9SLey Foon Tan return clk_hz; 367177ba1f9SLey Foon Tan } 368177ba1f9SLey Foon Tan 369177ba1f9SLey Foon Tan /* return 1 if PLL ramp is required */ 370177ba1f9SLey Foon Tan static int cm_is_pll_ramp_required(int main0periph1, 371177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 372177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg) 373177ba1f9SLey Foon Tan { 374177ba1f9SLey Foon Tan /* Check for main PLL */ 375177ba1f9SLey Foon Tan if (main0periph1 == 0) { 376177ba1f9SLey Foon Tan /* 377177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 378177ba1f9SLey Foon Tan * not sourced from main PLL 379177ba1f9SLey Foon Tan */ 380177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 381177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) 382177ba1f9SLey Foon Tan return 0; 383177ba1f9SLey Foon Tan 384177ba1f9SLey Foon Tan /* 385177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock is sourced from main PLL 386177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 387177ba1f9SLey Foon Tan */ 388177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 389177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 390177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 391177ba1f9SLey Foon Tan return 1; 392177ba1f9SLey Foon Tan 393177ba1f9SLey Foon Tan /* 394177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock is sourced from main PLL 395177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 396177ba1f9SLey Foon Tan */ 397177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && 398177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 399177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 400177ba1f9SLey Foon Tan return 2; 401177ba1f9SLey Foon Tan 402177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 403177ba1f9SLey Foon Tan /* 404177ba1f9SLey Foon Tan * PLL ramp is not required if both MPU clock and NOC clock are 405177ba1f9SLey Foon Tan * not sourced from periph PLL 406177ba1f9SLey Foon Tan */ 407177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 408177ba1f9SLey Foon Tan main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) 409177ba1f9SLey Foon Tan return 0; 410177ba1f9SLey Foon Tan 411177ba1f9SLey Foon Tan /* 412177ba1f9SLey Foon Tan * PLL ramp is required if MPU clock are source from periph PLL 413177ba1f9SLey Foon Tan * and MPU clock is over 900MHz (as advised by HW team) 414177ba1f9SLey Foon Tan */ 415177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 416177ba1f9SLey Foon Tan (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 417177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 418177ba1f9SLey Foon Tan return 1; 419177ba1f9SLey Foon Tan 420177ba1f9SLey Foon Tan /* 421177ba1f9SLey Foon Tan * PLL ramp is required if NOC clock are source from periph PLL 422177ba1f9SLey Foon Tan * and NOC clock is over 300MHz (as advised by HW team) 423177ba1f9SLey Foon Tan */ 424177ba1f9SLey Foon Tan if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && 425177ba1f9SLey Foon Tan (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 426177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 427177ba1f9SLey Foon Tan return 2; 428177ba1f9SLey Foon Tan } 429177ba1f9SLey Foon Tan 430177ba1f9SLey Foon Tan return 0; 431177ba1f9SLey Foon Tan } 432177ba1f9SLey Foon Tan 433177ba1f9SLey Foon Tan static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, 434177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 435177ba1f9SLey Foon Tan u32 safe_hz, u32 clk_hz) 436177ba1f9SLey Foon Tan { 437177ba1f9SLey Foon Tan u32 cnt; 438177ba1f9SLey Foon Tan u32 clk; 439177ba1f9SLey Foon Tan u32 shift; 440177ba1f9SLey Foon Tan u32 mask; 441177ba1f9SLey Foon Tan u32 denom; 442177ba1f9SLey Foon Tan 443177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 444177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 445177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 446177ba1f9SLey Foon Tan shift = 0; 447177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 448177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 449177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 450177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 451177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 452177ba1f9SLey Foon Tan shift = 0; 453177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 454177ba1f9SLey Foon Tan denom = main_cfg->vco1_denom; 455177ba1f9SLey Foon Tan } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 456177ba1f9SLey Foon Tan cnt = main_cfg->mpuclk_cnt; 457177ba1f9SLey Foon Tan clk = main_cfg->mpuclk; 458177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; 459177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 460177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 461177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 462177ba1f9SLey Foon Tan cnt = main_cfg->nocclk_cnt; 463177ba1f9SLey Foon Tan clk = main_cfg->nocclk; 464177ba1f9SLey Foon Tan shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; 465177ba1f9SLey Foon Tan mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 466177ba1f9SLey Foon Tan denom = per_cfg->vco1_denom; 467177ba1f9SLey Foon Tan } else { 468177ba1f9SLey Foon Tan return 0; 469177ba1f9SLey Foon Tan } 470177ba1f9SLey Foon Tan 471177ba1f9SLey Foon Tan return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * 472177ba1f9SLey Foon Tan (1 + denom) - 1; 473177ba1f9SLey Foon Tan } 474177ba1f9SLey Foon Tan 475177ba1f9SLey Foon Tan /* 476177ba1f9SLey Foon Tan * Calculate the new PLL numerator which is based on existing DTS hand off and 477177ba1f9SLey Foon Tan * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the 478177ba1f9SLey Foon Tan * numerator while maintaining denominator as denominator will influence the 479177ba1f9SLey Foon Tan * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final 480177ba1f9SLey Foon Tan * value for numerator is minus with 1 to cater our register value 481177ba1f9SLey Foon Tan * representation. 482177ba1f9SLey Foon Tan */ 483177ba1f9SLey Foon Tan static unsigned int cm_calc_safe_pll_numer(int main0periph1, 484177ba1f9SLey Foon Tan struct mainpll_cfg *main_cfg, 485177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 486177ba1f9SLey Foon Tan unsigned int safe_hz) 487177ba1f9SLey Foon Tan { 488177ba1f9SLey Foon Tan unsigned int clk_hz = 0; 489177ba1f9SLey Foon Tan 490177ba1f9SLey Foon Tan /* Check for main PLL */ 491177ba1f9SLey Foon Tan if (main0periph1 == 0) { 492177ba1f9SLey Foon Tan /* Check main VCO clock source: eosc, intosc or f2s? */ 493177ba1f9SLey Foon Tan switch (main_cfg->vco0_psrc) { 494177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 495177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 496177ba1f9SLey Foon Tan break; 497177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 498177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 499177ba1f9SLey Foon Tan break; 500177ba1f9SLey Foon Tan case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 501177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 502177ba1f9SLey Foon Tan break; 503177ba1f9SLey Foon Tan default: 504177ba1f9SLey Foon Tan return 0; 505177ba1f9SLey Foon Tan } 506177ba1f9SLey Foon Tan } else if (main0periph1 == 1) { 507177ba1f9SLey Foon Tan /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ 508177ba1f9SLey Foon Tan switch (per_cfg->vco0_psrc) { 509177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 510177ba1f9SLey Foon Tan clk_hz = eosc1_hz; 511177ba1f9SLey Foon Tan break; 512177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 513177ba1f9SLey Foon Tan clk_hz = cb_intosc_hz; 514177ba1f9SLey Foon Tan break; 515177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_F2S: 516177ba1f9SLey Foon Tan clk_hz = f2s_free_hz; 517177ba1f9SLey Foon Tan break; 518177ba1f9SLey Foon Tan case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 519177ba1f9SLey Foon Tan clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 520177ba1f9SLey Foon Tan clk_hz /= main_cfg->cntr15clk_cnt; 521177ba1f9SLey Foon Tan break; 522177ba1f9SLey Foon Tan default: 523177ba1f9SLey Foon Tan return 0; 524177ba1f9SLey Foon Tan } 525177ba1f9SLey Foon Tan } else { 526177ba1f9SLey Foon Tan return 0; 527177ba1f9SLey Foon Tan } 528177ba1f9SLey Foon Tan 529177ba1f9SLey Foon Tan return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); 530177ba1f9SLey Foon Tan } 531177ba1f9SLey Foon Tan 532177ba1f9SLey Foon Tan /* ramping the main PLL to final value */ 533177ba1f9SLey Foon Tan static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, 534177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 535177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz) 536177ba1f9SLey Foon Tan { 537177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 538177ba1f9SLey Foon Tan 539177ba1f9SLey Foon Tan /* find out the increment value */ 540177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 541177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 542177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 543177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 544177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 545177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 546177ba1f9SLey Foon Tan } 547177ba1f9SLey Foon Tan 548177ba1f9SLey Foon Tan /* execute the ramping here */ 549177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_main_hz + clk_incr_hz; 550177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 551177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << 552177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 553177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), 554177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 555177ba1f9SLey Foon Tan mdelay(1); 556177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 557177ba1f9SLey Foon Tan } 558177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 559177ba1f9SLey Foon Tan main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); 560177ba1f9SLey Foon Tan mdelay(1); 561177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 562177ba1f9SLey Foon Tan } 563177ba1f9SLey Foon Tan 564177ba1f9SLey Foon Tan /* ramping the periph PLL to final value */ 565177ba1f9SLey Foon Tan static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, 566177ba1f9SLey Foon Tan struct perpll_cfg *per_cfg, 567177ba1f9SLey Foon Tan unsigned int pll_ramp_periph_hz) 568177ba1f9SLey Foon Tan { 569177ba1f9SLey Foon Tan unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 570177ba1f9SLey Foon Tan 571177ba1f9SLey Foon Tan /* find out the increment value */ 572177ba1f9SLey Foon Tan if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 573177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 574177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 575177ba1f9SLey Foon Tan } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 576177ba1f9SLey Foon Tan clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 577177ba1f9SLey Foon Tan clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 578177ba1f9SLey Foon Tan } 579177ba1f9SLey Foon Tan /* execute the ramping here */ 580177ba1f9SLey Foon Tan for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; 581177ba1f9SLey Foon Tan clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 582177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 583177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), 584177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 585177ba1f9SLey Foon Tan mdelay(1); 586177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 587177ba1f9SLey Foon Tan } 588177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 589177ba1f9SLey Foon Tan per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); 590177ba1f9SLey Foon Tan mdelay(1); 591177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 592177ba1f9SLey Foon Tan } 593177ba1f9SLey Foon Tan 594177ba1f9SLey Foon Tan /* 595177ba1f9SLey Foon Tan * Setup clocks while making no assumptions of the 596177ba1f9SLey Foon Tan * previous state of the clocks. 597177ba1f9SLey Foon Tan * 598177ba1f9SLey Foon Tan * Start by being paranoid and gate all sw managed clocks 599177ba1f9SLey Foon Tan * 600177ba1f9SLey Foon Tan * Put all plls in bypass 601177ba1f9SLey Foon Tan * 602177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value (bgpwr dwn). 603177ba1f9SLey Foon Tan * 604177ba1f9SLey Foon Tan * Put peripheral and main pll src to reset value to avoid glitch. 605177ba1f9SLey Foon Tan * 606177ba1f9SLey Foon Tan * Delay 5 us. 607177ba1f9SLey Foon Tan * 608177ba1f9SLey Foon Tan * Deassert bg pwr dn and set numerator and denominator 609177ba1f9SLey Foon Tan * 610177ba1f9SLey Foon Tan * Start 7 us timer. 611177ba1f9SLey Foon Tan * 612177ba1f9SLey Foon Tan * set internal dividers 613177ba1f9SLey Foon Tan * 614177ba1f9SLey Foon Tan * Wait for 7 us timer. 615177ba1f9SLey Foon Tan * 616177ba1f9SLey Foon Tan * Enable plls 617177ba1f9SLey Foon Tan * 618177ba1f9SLey Foon Tan * Set external dividers while plls are locking 619177ba1f9SLey Foon Tan * 620177ba1f9SLey Foon Tan * Wait for pll lock 621177ba1f9SLey Foon Tan * 622177ba1f9SLey Foon Tan * Assert/deassert outreset all. 623177ba1f9SLey Foon Tan * 624177ba1f9SLey Foon Tan * Take all pll's out of bypass 625177ba1f9SLey Foon Tan * 626177ba1f9SLey Foon Tan * Clear safe mode 627177ba1f9SLey Foon Tan * 628177ba1f9SLey Foon Tan * set source main and peripheral clocks 629177ba1f9SLey Foon Tan * 630177ba1f9SLey Foon Tan * Ungate clocks 631177ba1f9SLey Foon Tan */ 632177ba1f9SLey Foon Tan 633177ba1f9SLey Foon Tan static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 634177ba1f9SLey Foon Tan { 635177ba1f9SLey Foon Tan unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, 636177ba1f9SLey Foon Tan ramp_required; 637177ba1f9SLey Foon Tan 638177ba1f9SLey Foon Tan /* gate off all mainpll clock excpet HW managed clock */ 639177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 640177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 641177ba1f9SLey Foon Tan &clock_manager_base->main_pll.enr); 642177ba1f9SLey Foon Tan 643177ba1f9SLey Foon Tan /* now we can gate off the rest of the peripheral clocks */ 644177ba1f9SLey Foon Tan writel(0, &clock_manager_base->per_pll.en); 645177ba1f9SLey Foon Tan 646177ba1f9SLey Foon Tan /* Put all plls in external bypass */ 647177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 648177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypasss); 649177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 650177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypasss); 651177ba1f9SLey Foon Tan 652177ba1f9SLey Foon Tan /* 653177ba1f9SLey Foon Tan * Put all plls VCO registers back to reset value. 654177ba1f9SLey Foon Tan * Some code might have messed with them. At same time set the 655177ba1f9SLey Foon Tan * desired clock source 656177ba1f9SLey Foon Tan */ 657177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO0_RESET | 658177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | 659177ba1f9SLey Foon Tan (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), 660177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 661177ba1f9SLey Foon Tan 662177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO0_RESET | 663177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | 664177ba1f9SLey Foon Tan (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), 665177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 666177ba1f9SLey Foon Tan 667177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); 668177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); 669177ba1f9SLey Foon Tan 670177ba1f9SLey Foon Tan /* clear the interrupt register status register */ 671177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 672177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 673177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 674177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 675177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 676177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | 677177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | 678177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, 679177ba1f9SLey Foon Tan &clock_manager_base->intr); 680177ba1f9SLey Foon Tan 681177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for main PLL */ 682177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); 683177ba1f9SLey Foon Tan if (ramp_required) { 684177ba1f9SLey Foon Tan /* set main PLL to safe starting threshold frequency */ 685177ba1f9SLey Foon Tan if (ramp_required == 1) 686177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 687177ba1f9SLey Foon Tan else if (ramp_required == 2) 688177ba1f9SLey Foon Tan pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 689177ba1f9SLey Foon Tan 690177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 691177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(0, main_cfg, per_cfg, 692177ba1f9SLey Foon Tan pll_ramp_main_hz), 693177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 694177ba1f9SLey Foon Tan } else 695177ba1f9SLey Foon Tan writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 696177ba1f9SLey Foon Tan main_cfg->vco1_numer, 697177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco1); 698177ba1f9SLey Foon Tan 699177ba1f9SLey Foon Tan /* Program VCO Numerator and Denominator for periph PLL */ 700177ba1f9SLey Foon Tan ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); 701177ba1f9SLey Foon Tan if (ramp_required) { 702177ba1f9SLey Foon Tan /* set periph PLL to safe starting threshold frequency */ 703177ba1f9SLey Foon Tan if (ramp_required == 1) 704177ba1f9SLey Foon Tan pll_ramp_periph_hz = 705177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 706177ba1f9SLey Foon Tan else if (ramp_required == 2) 707177ba1f9SLey Foon Tan pll_ramp_periph_hz = 708177ba1f9SLey Foon Tan CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 709177ba1f9SLey Foon Tan 710177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 711177ba1f9SLey Foon Tan cm_calc_safe_pll_numer(1, main_cfg, per_cfg, 712177ba1f9SLey Foon Tan pll_ramp_periph_hz), 713177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 714177ba1f9SLey Foon Tan } else 715177ba1f9SLey Foon Tan writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 716177ba1f9SLey Foon Tan per_cfg->vco1_numer, 717177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco1); 718177ba1f9SLey Foon Tan 719177ba1f9SLey Foon Tan /* Wait for at least 5 us */ 720177ba1f9SLey Foon Tan udelay(5); 721177ba1f9SLey Foon Tan 722177ba1f9SLey Foon Tan /* Now deassert BGPWRDN and PWRDN */ 723177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 724177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | 725177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); 726177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 727177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | 728177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); 729177ba1f9SLey Foon Tan 730177ba1f9SLey Foon Tan /* Wait for at least 7 us */ 731177ba1f9SLey Foon Tan udelay(7); 732177ba1f9SLey Foon Tan 733177ba1f9SLey Foon Tan /* enable the VCO and disable the external regulator to PLL */ 734177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->main_pll.vco0) & 735177ba1f9SLey Foon Tan ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | 736177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_EN_SET_MSK, 737177ba1f9SLey Foon Tan &clock_manager_base->main_pll.vco0); 738177ba1f9SLey Foon Tan writel((readl(&clock_manager_base->per_pll.vco0) & 739177ba1f9SLey Foon Tan ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | 740177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_EN_SET_MSK, 741177ba1f9SLey Foon Tan &clock_manager_base->per_pll.vco0); 742177ba1f9SLey Foon Tan 743177ba1f9SLey Foon Tan /* setup all the main PLL counter and clock source */ 744177ba1f9SLey Foon Tan writel(main_cfg->nocclk, 745177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); 746177ba1f9SLey Foon Tan writel(main_cfg->mpuclk, 747177ba1f9SLey Foon Tan SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); 748177ba1f9SLey Foon Tan 749177ba1f9SLey Foon Tan /* main_emaca_clk divider */ 750177ba1f9SLey Foon Tan writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); 751177ba1f9SLey Foon Tan /* main_emacb_clk divider */ 752177ba1f9SLey Foon Tan writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); 753177ba1f9SLey Foon Tan /* main_emac_ptp_clk divider */ 754177ba1f9SLey Foon Tan writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); 755177ba1f9SLey Foon Tan /* main_gpio_db_clk divider */ 756177ba1f9SLey Foon Tan writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); 757177ba1f9SLey Foon Tan /* main_sdmmc_clk divider */ 758177ba1f9SLey Foon Tan writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); 759177ba1f9SLey Foon Tan /* main_s2f_user0_clk divider */ 760177ba1f9SLey Foon Tan writel(main_cfg->cntr7clk_cnt | 761177ba1f9SLey Foon Tan (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), 762177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr7clk); 763177ba1f9SLey Foon Tan /* main_s2f_user1_clk divider */ 764177ba1f9SLey Foon Tan writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); 765177ba1f9SLey Foon Tan /* main_hmc_pll_clk divider */ 766177ba1f9SLey Foon Tan writel(main_cfg->cntr9clk_cnt | 767177ba1f9SLey Foon Tan (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), 768177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr9clk); 769177ba1f9SLey Foon Tan /* main_periph_ref_clk divider */ 770177ba1f9SLey Foon Tan writel(main_cfg->cntr15clk_cnt, 771177ba1f9SLey Foon Tan &clock_manager_base->main_pll.cntr15clk); 772177ba1f9SLey Foon Tan 773177ba1f9SLey Foon Tan /* setup all the peripheral PLL counter and clock source */ 774177ba1f9SLey Foon Tan /* peri_emaca_clk divider */ 775177ba1f9SLey Foon Tan writel(per_cfg->cntr2clk_cnt | 776177ba1f9SLey Foon Tan (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), 777177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr2clk); 778177ba1f9SLey Foon Tan /* peri_emacb_clk divider */ 779177ba1f9SLey Foon Tan writel(per_cfg->cntr3clk_cnt | 780177ba1f9SLey Foon Tan (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), 781177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr3clk); 782177ba1f9SLey Foon Tan /* peri_emac_ptp_clk divider */ 783177ba1f9SLey Foon Tan writel(per_cfg->cntr4clk_cnt | 784177ba1f9SLey Foon Tan (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), 785177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr4clk); 786177ba1f9SLey Foon Tan /* peri_gpio_db_clk divider */ 787177ba1f9SLey Foon Tan writel(per_cfg->cntr5clk_cnt | 788177ba1f9SLey Foon Tan (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), 789177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr5clk); 790177ba1f9SLey Foon Tan /* peri_sdmmc_clk divider */ 791177ba1f9SLey Foon Tan writel(per_cfg->cntr6clk_cnt | 792177ba1f9SLey Foon Tan (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), 793177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr6clk); 794177ba1f9SLey Foon Tan /* peri_s2f_user0_clk divider */ 795177ba1f9SLey Foon Tan writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); 796177ba1f9SLey Foon Tan /* peri_s2f_user1_clk divider */ 797177ba1f9SLey Foon Tan writel(per_cfg->cntr8clk_cnt | 798177ba1f9SLey Foon Tan (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), 799177ba1f9SLey Foon Tan &clock_manager_base->per_pll.cntr8clk); 800177ba1f9SLey Foon Tan /* peri_hmc_pll_clk divider */ 801177ba1f9SLey Foon Tan writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); 802177ba1f9SLey Foon Tan 803177ba1f9SLey Foon Tan /* setup all the external PLL counter */ 804177ba1f9SLey Foon Tan /* mpu wrapper / external divider */ 805177ba1f9SLey Foon Tan writel(main_cfg->mpuclk_cnt | 806177ba1f9SLey Foon Tan (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), 807177ba1f9SLey Foon Tan &clock_manager_base->main_pll.mpuclk); 808177ba1f9SLey Foon Tan /* NOC wrapper / external divider */ 809177ba1f9SLey Foon Tan writel(main_cfg->nocclk_cnt | 810177ba1f9SLey Foon Tan (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), 811177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocclk); 812177ba1f9SLey Foon Tan /* NOC subclock divider such as l4 */ 813177ba1f9SLey Foon Tan writel(main_cfg->nocdiv_l4mainclk | 814177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4mpclk << 815177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | 816177ba1f9SLey Foon Tan (main_cfg->nocdiv_l4spclk << 817177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | 818177ba1f9SLey Foon Tan (main_cfg->nocdiv_csatclk << 819177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | 820177ba1f9SLey Foon Tan (main_cfg->nocdiv_cstraceclk << 821177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | 822177ba1f9SLey Foon Tan (main_cfg->nocdiv_cspdbclk << 823177ba1f9SLey Foon Tan CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), 824177ba1f9SLey Foon Tan &clock_manager_base->main_pll.nocdiv); 825177ba1f9SLey Foon Tan /* gpio_db external divider */ 826177ba1f9SLey Foon Tan writel(per_cfg->gpiodiv_gpiodbclk, 827177ba1f9SLey Foon Tan &clock_manager_base->per_pll.gpiodiv); 828177ba1f9SLey Foon Tan 829177ba1f9SLey Foon Tan /* setup the EMAC clock mux select */ 830177ba1f9SLey Foon Tan writel((per_cfg->emacctl_emac0sel << 831177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | 832177ba1f9SLey Foon Tan (per_cfg->emacctl_emac1sel << 833177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | 834177ba1f9SLey Foon Tan (per_cfg->emacctl_emac2sel << 835177ba1f9SLey Foon Tan CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), 836177ba1f9SLey Foon Tan &clock_manager_base->per_pll.emacctl); 837177ba1f9SLey Foon Tan 838177ba1f9SLey Foon Tan /* at this stage, check for PLL lock status */ 839177ba1f9SLey Foon Tan cm_wait_for_lock(LOCKED_MASK); 840177ba1f9SLey Foon Tan 841177ba1f9SLey Foon Tan /* 842177ba1f9SLey Foon Tan * after locking, but before taking out of bypass, 843177ba1f9SLey Foon Tan * assert/deassert outresetall 844177ba1f9SLey Foon Tan */ 845177ba1f9SLey Foon Tan /* assert mainpll outresetall */ 846177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->main_pll.vco0, 847177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 848177ba1f9SLey Foon Tan /* assert perpll outresetall */ 849177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->per_pll.vco0, 850177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 851177ba1f9SLey Foon Tan /* de-assert mainpll outresetall */ 852177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->main_pll.vco0, 853177ba1f9SLey Foon Tan CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 854177ba1f9SLey Foon Tan /* de-assert perpll outresetall */ 855177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->per_pll.vco0, 856177ba1f9SLey Foon Tan CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 857177ba1f9SLey Foon Tan 858177ba1f9SLey Foon Tan /* Take all PLLs out of bypass when boot mode is cleared. */ 859177ba1f9SLey Foon Tan /* release mainpll from bypass */ 860177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_BYPASS_RESET, 861177ba1f9SLey Foon Tan &clock_manager_base->main_pll.bypassr); 862177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 863177ba1f9SLey Foon Tan cm_wait_for_fsm(); 864177ba1f9SLey Foon Tan 865177ba1f9SLey Foon Tan /* release perpll from bypass */ 866177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_BYPASS_RESET, 867177ba1f9SLey Foon Tan &clock_manager_base->per_pll.bypassr); 868177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 869177ba1f9SLey Foon Tan cm_wait_for_fsm(); 870177ba1f9SLey Foon Tan 871177ba1f9SLey Foon Tan /* clear boot mode */ 872177ba1f9SLey Foon Tan clrbits_le32(&clock_manager_base->ctrl, 873177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); 874177ba1f9SLey Foon Tan /* wait till Clock Manager is not busy */ 875177ba1f9SLey Foon Tan cm_wait_for_fsm(); 876177ba1f9SLey Foon Tan 877177ba1f9SLey Foon Tan /* At here, we need to ramp to final value if needed */ 878177ba1f9SLey Foon Tan if (pll_ramp_main_hz != 0) 879177ba1f9SLey Foon Tan cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); 880177ba1f9SLey Foon Tan if (pll_ramp_periph_hz != 0) 881177ba1f9SLey Foon Tan cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); 882177ba1f9SLey Foon Tan 883177ba1f9SLey Foon Tan /* Now ungate non-hw-managed clocks */ 884177ba1f9SLey Foon Tan writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 885177ba1f9SLey Foon Tan CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 886177ba1f9SLey Foon Tan &clock_manager_base->main_pll.ens); 887177ba1f9SLey Foon Tan writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); 888177ba1f9SLey Foon Tan 889177ba1f9SLey Foon Tan /* Clear the loss lock and slip bits as they might set during 890177ba1f9SLey Foon Tan clock reconfiguration */ 891177ba1f9SLey Foon Tan writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 892177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 893177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 894177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 895177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 896177ba1f9SLey Foon Tan CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, 897177ba1f9SLey Foon Tan &clock_manager_base->intr); 898177ba1f9SLey Foon Tan 899177ba1f9SLey Foon Tan return 0; 900177ba1f9SLey Foon Tan } 901177ba1f9SLey Foon Tan 902*0b8f6378SMarek Vasut static void cm_use_intosc(void) 903177ba1f9SLey Foon Tan { 904177ba1f9SLey Foon Tan setbits_le32(&clock_manager_base->ctrl, 905177ba1f9SLey Foon Tan CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); 906177ba1f9SLey Foon Tan } 907177ba1f9SLey Foon Tan 908177ba1f9SLey Foon Tan int cm_basic_init(const void *blob) 909177ba1f9SLey Foon Tan { 910177ba1f9SLey Foon Tan struct mainpll_cfg main_cfg; 911177ba1f9SLey Foon Tan struct perpll_cfg per_cfg; 912177ba1f9SLey Foon Tan int rval; 913177ba1f9SLey Foon Tan 914177ba1f9SLey Foon Tan /* initialize to zero for use case of optional node */ 915177ba1f9SLey Foon Tan memset(&main_cfg, 0, sizeof(main_cfg)); 916177ba1f9SLey Foon Tan memset(&per_cfg, 0, sizeof(per_cfg)); 917177ba1f9SLey Foon Tan 918480f7f9cSMarek Vasut rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); 919177ba1f9SLey Foon Tan if (rval) 920177ba1f9SLey Foon Tan return rval; 921177ba1f9SLey Foon Tan 922*0b8f6378SMarek Vasut cm_use_intosc(); 923*0b8f6378SMarek Vasut 924f4c3e0dcSMarek Vasut return cm_full_cfg(&main_cfg, &per_cfg); 925177ba1f9SLey Foon Tan } 926*0b8f6378SMarek Vasut #endif 927177ba1f9SLey Foon Tan 928d81b5da3SMarek Vasut static u32 cm_get_rate_dm(char *name) 929d81b5da3SMarek Vasut { 930d81b5da3SMarek Vasut struct uclass *uc; 931d81b5da3SMarek Vasut struct udevice *dev = NULL; 932d81b5da3SMarek Vasut struct clk clk = { 0 }; 933d81b5da3SMarek Vasut ulong rate; 934d81b5da3SMarek Vasut int ret; 935d81b5da3SMarek Vasut 936d81b5da3SMarek Vasut /* Device addresses start at 1 */ 937d81b5da3SMarek Vasut ret = uclass_get(UCLASS_CLK, &uc); 938d81b5da3SMarek Vasut if (ret) 939d81b5da3SMarek Vasut return 0; 940d81b5da3SMarek Vasut 941d81b5da3SMarek Vasut ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev); 942d81b5da3SMarek Vasut if (ret) 943d81b5da3SMarek Vasut return 0; 944d81b5da3SMarek Vasut 945d81b5da3SMarek Vasut ret = device_probe(dev); 946d81b5da3SMarek Vasut if (ret) 947d81b5da3SMarek Vasut return 0; 948d81b5da3SMarek Vasut 949d81b5da3SMarek Vasut ret = clk_request(dev, &clk); 950d81b5da3SMarek Vasut if (ret) 951d81b5da3SMarek Vasut return 0; 952d81b5da3SMarek Vasut 953d81b5da3SMarek Vasut rate = clk_get_rate(&clk); 954d81b5da3SMarek Vasut 955d81b5da3SMarek Vasut clk_free(&clk); 956d81b5da3SMarek Vasut 957d81b5da3SMarek Vasut return rate; 958d81b5da3SMarek Vasut } 959d81b5da3SMarek Vasut 960d81b5da3SMarek Vasut static u32 cm_get_rate_dm_khz(char *name) 961d81b5da3SMarek Vasut { 962d81b5da3SMarek Vasut return cm_get_rate_dm(name) / 1000; 963d81b5da3SMarek Vasut } 964d81b5da3SMarek Vasut 965177ba1f9SLey Foon Tan unsigned long cm_get_mpu_clk_hz(void) 966177ba1f9SLey Foon Tan { 967d81b5da3SMarek Vasut return cm_get_rate_dm("main_mpu_base_clk"); 968177ba1f9SLey Foon Tan } 969177ba1f9SLey Foon Tan 970177ba1f9SLey Foon Tan unsigned int cm_get_qspi_controller_clk_hz(void) 971177ba1f9SLey Foon Tan { 972d81b5da3SMarek Vasut return cm_get_rate_dm("qspi_clk"); 973177ba1f9SLey Foon Tan } 974177ba1f9SLey Foon Tan 975d81b5da3SMarek Vasut unsigned int cm_get_l4_sp_clk_hz(void) 97621143ce1SEugeniy Paltsev { 977d81b5da3SMarek Vasut return cm_get_rate_dm("l4_sp_clk"); 97821143ce1SEugeniy Paltsev } 97921143ce1SEugeniy Paltsev 980177ba1f9SLey Foon Tan void cm_print_clock_quick_summary(void) 981177ba1f9SLey Foon Tan { 982d81b5da3SMarek Vasut printf("MPU %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk")); 983d81b5da3SMarek Vasut printf("MMC %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk")); 984d81b5da3SMarek Vasut printf("QSPI %8d kHz\n", cm_get_rate_dm_khz("qspi_clk")); 985d81b5da3SMarek Vasut printf("SPI %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk")); 986d81b5da3SMarek Vasut printf("EOSC1 %8d kHz\n", cm_get_rate_dm_khz("osc1")); 987d81b5da3SMarek Vasut printf("cb_intosc %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk")); 988d81b5da3SMarek Vasut printf("f2s_free %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk")); 989d81b5da3SMarek Vasut printf("Main VCO %8d kHz\n", cm_get_rate_dm_khz("main_pll@40")); 990d81b5da3SMarek Vasut printf("NOC %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk")); 991d81b5da3SMarek Vasut printf("L4 Main %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk")); 992d81b5da3SMarek Vasut printf("L4 MP %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk")); 993d81b5da3SMarek Vasut printf("L4 SP %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk")); 994d81b5da3SMarek Vasut printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk")); 995177ba1f9SLey Foon Tan } 996