1 /* 2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <wait_bit.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock_manager.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 static const struct socfpga_clock_manager *clock_manager_base = 15 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 16 17 void cm_wait_for_lock(u32 mask) 18 { 19 u32 inter_val; 20 u32 retry = 0; 21 do { 22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 23 inter_val = readl(&clock_manager_base->inter) & mask; 24 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 25 inter_val = readl(&clock_manager_base->stat) & mask; 26 #endif 27 /* Wait for stable lock */ 28 if (inter_val == mask) 29 retry++; 30 else 31 retry = 0; 32 if (retry >= 10) 33 break; 34 } while (1); 35 } 36 37 /* function to poll in the fsm busy bit */ 38 int cm_wait_for_fsm(void) 39 { 40 return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat, 41 CLKMGR_STAT_BUSY, false, 20000, false); 42 } 43 44 int set_cpu_clk_info(void) 45 { 46 /* Calculate the clock frequencies required for drivers */ 47 cm_get_l4_sp_clk_hz(); 48 cm_get_mmc_controller_clk_hz(); 49 50 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; 51 gd->bd->bi_dsp_freq = 0; 52 53 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 54 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; 55 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 56 gd->bd->bi_ddr_freq = 0; 57 #endif 58 59 return 0; 60 } 61 62 int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 63 { 64 cm_print_clock_quick_summary(); 65 return 0; 66 } 67 68 U_BOOT_CMD( 69 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, 70 "display clocks", 71 "" 72 ); 73