1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #include <common.h>
7 #include <wait_bit.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock_manager.h>
10 
11 DECLARE_GLOBAL_DATA_PTR;
12 
13 static const struct socfpga_clock_manager *clock_manager_base =
14 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
15 
16 void cm_wait_for_lock(u32 mask)
17 {
18 	u32 inter_val;
19 	u32 retry = 0;
20 	do {
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 		inter_val = readl(&clock_manager_base->inter) & mask;
23 #else
24 		inter_val = readl(&clock_manager_base->stat) & mask;
25 #endif
26 		/* Wait for stable lock */
27 		if (inter_val == mask)
28 			retry++;
29 		else
30 			retry = 0;
31 		if (retry >= 10)
32 			break;
33 	} while (1);
34 }
35 
36 /* function to poll in the fsm busy bit */
37 int cm_wait_for_fsm(void)
38 {
39 	return wait_for_bit_le32(&clock_manager_base->stat,
40 				 CLKMGR_STAT_BUSY, false, 20000, false);
41 }
42 
43 int set_cpu_clk_info(void)
44 {
45 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
46 	/* Calculate the clock frequencies required for drivers */
47 	cm_get_l4_sp_clk_hz();
48 	cm_get_mmc_controller_clk_hz();
49 #endif
50 
51 	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
52 	gd->bd->bi_dsp_freq = 0;
53 
54 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
55 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
56 #else
57 	gd->bd->bi_ddr_freq = 0;
58 #endif
59 
60 	return 0;
61 }
62 
63 #ifndef CONFIG_SPL_BUILD
64 static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
65 {
66 	cm_print_clock_quick_summary();
67 	return 0;
68 }
69 
70 U_BOOT_CMD(
71 	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
72 	"display clocks",
73 	""
74 );
75 #endif
76