1 /*
2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock_manager.h>
10 
11 DECLARE_GLOBAL_DATA_PTR;
12 
13 static const struct socfpga_clock_manager *clock_manager_base =
14 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
15 
16 static void cm_wait_for_lock(uint32_t mask)
17 {
18 	register uint32_t inter_val;
19 	uint32_t retry = 0;
20 	do {
21 		inter_val = readl(&clock_manager_base->inter) & mask;
22 		if (inter_val == mask)
23 			retry++;
24 		else
25 			retry = 0;
26 		if (retry >= 10)
27 			break;
28 	} while (1);
29 }
30 
31 /* function to poll in the fsm busy bit */
32 static void cm_wait_for_fsm(void)
33 {
34 	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
35 		;
36 }
37 
38 /*
39  * function to write the bypass register which requires a poll of the
40  * busy bit
41  */
42 static void cm_write_bypass(uint32_t val)
43 {
44 	writel(val, &clock_manager_base->bypass);
45 	cm_wait_for_fsm();
46 }
47 
48 /* function to write the ctrl register which requires a poll of the busy bit */
49 static void cm_write_ctrl(uint32_t val)
50 {
51 	writel(val, &clock_manager_base->ctrl);
52 	cm_wait_for_fsm();
53 }
54 
55 /* function to write a clock register that has phase information */
56 static void cm_write_with_phase(uint32_t value,
57 				uint32_t reg_address, uint32_t mask)
58 {
59 	/* poll until phase is zero */
60 	while (readl(reg_address) & mask)
61 		;
62 
63 	writel(value, reg_address);
64 
65 	while (readl(reg_address) & mask)
66 		;
67 }
68 
69 /*
70  * Setup clocks while making no assumptions about previous state of the clocks.
71  *
72  * Start by being paranoid and gate all sw managed clocks
73  * Put all plls in bypass
74  * Put all plls VCO registers back to reset value (bandgap power down).
75  * Put peripheral and main pll src to reset value to avoid glitch.
76  * Delay 5 us.
77  * Deassert bandgap power down and set numerator and denominator
78  * Start 7 us timer.
79  * set internal dividers
80  * Wait for 7 us timer.
81  * Enable plls
82  * Set external dividers while plls are locking
83  * Wait for pll lock
84  * Assert/deassert outreset all.
85  * Take all pll's out of bypass
86  * Clear safe mode
87  * set source main and peripheral clocks
88  * Ungate clocks
89  */
90 
91 void cm_basic_init(const struct cm_config * const cfg)
92 {
93 	uint32_t start, timeout;
94 
95 	/* Start by being paranoid and gate all sw managed clocks */
96 
97 	/*
98 	 * We need to disable nandclk
99 	 * and then do another apb access before disabling
100 	 * gatting off the rest of the periperal clocks.
101 	 */
102 	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
103 		readl(&clock_manager_base->per_pll.en),
104 		&clock_manager_base->per_pll.en);
105 
106 	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
107 	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
108 		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
109 		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
110 		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
111 		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
112 		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
113 		&clock_manager_base->main_pll.en);
114 
115 	writel(0, &clock_manager_base->sdr_pll.en);
116 
117 	/* now we can gate off the rest of the peripheral clocks */
118 	writel(0, &clock_manager_base->per_pll.en);
119 
120 	/* Put all plls in bypass */
121 	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
122 			CLKMGR_BYPASS_MAINPLL);
123 
124 	/* Put all plls VCO registers back to reset value. */
125 	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
126 	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
127 	       &clock_manager_base->main_pll.vco);
128 	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
129 	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
130 	       &clock_manager_base->per_pll.vco);
131 	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
132 	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
133 	       &clock_manager_base->sdr_pll.vco);
134 
135 	/*
136 	 * The clocks to the flash devices and the L4_MAIN clocks can
137 	 * glitch when coming out of safe mode if their source values
138 	 * are different from their reset value.  So the trick it to
139 	 * put them back to their reset state, and change input
140 	 * after exiting safe mode but before ungating the clocks.
141 	 */
142 	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
143 	       &clock_manager_base->per_pll.src);
144 	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
145 	       &clock_manager_base->main_pll.l4src);
146 
147 	/* read back for the required 5 us delay. */
148 	readl(&clock_manager_base->main_pll.vco);
149 	readl(&clock_manager_base->per_pll.vco);
150 	readl(&clock_manager_base->sdr_pll.vco);
151 
152 
153 	/*
154 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
155 	 * with numerator and denominator.
156 	 */
157 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
158 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
159 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
160 
161 	/*
162 	 * Time starts here
163 	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
164 	 */
165 	start = get_timer(0);
166 	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
167 	timeout = 7;
168 
169 	/* main mpu */
170 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
171 
172 	/* main main clock */
173 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
174 
175 	/* main for dbg */
176 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
177 
178 	/* main for cfgs2fuser0clk */
179 	writel(cfg->cfg2fuser0clk,
180 	       &clock_manager_base->main_pll.cfgs2fuser0clk);
181 
182 	/* Peri emac0 50 MHz default to RMII */
183 	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
184 
185 	/* Peri emac1 50 MHz default to RMII */
186 	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
187 
188 	/* Peri QSPI */
189 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
190 
191 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
192 
193 	/* Peri pernandsdmmcclk */
194 	writel(cfg->mainnandsdmmcclk,
195 	       &clock_manager_base->main_pll.mainnandsdmmcclk);
196 
197 	writel(cfg->pernandsdmmcclk,
198 	       &clock_manager_base->per_pll.pernandsdmmcclk);
199 
200 	/* Peri perbaseclk */
201 	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
202 
203 	/* Peri s2fuser1clk */
204 	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
205 
206 	/* 7 us must have elapsed before we can enable the VCO */
207 	while (get_timer(start) < timeout)
208 		;
209 
210 	/* Enable vco */
211 	/* main pll vco */
212 	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
213 	       &clock_manager_base->main_pll.vco);
214 
215 	/* periferal pll */
216 	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
217 	       &clock_manager_base->per_pll.vco);
218 
219 	/* sdram pll vco */
220 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
221 	       &clock_manager_base->sdr_pll.vco);
222 
223 	/* L3 MP and L3 SP */
224 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
225 
226 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
227 
228 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
229 
230 	/* L4 MP, L4 SP, can0, and can1 */
231 	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
232 
233 	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
234 
235 #define LOCKED_MASK \
236 	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
237 	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
238 	CLKMGR_INTER_MAINPLLLOCKED_MASK)
239 
240 	cm_wait_for_lock(LOCKED_MASK);
241 
242 	/* write the sdram clock counters before toggling outreset all */
243 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
244 	       &clock_manager_base->sdr_pll.ddrdqsclk);
245 
246 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
247 	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
248 
249 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
250 	       &clock_manager_base->sdr_pll.ddrdqclk);
251 
252 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
253 	       &clock_manager_base->sdr_pll.s2fuser2clk);
254 
255 	/*
256 	 * after locking, but before taking out of bypass
257 	 * assert/deassert outresetall
258 	 */
259 	uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
260 
261 	/* assert main outresetall */
262 	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
263 	       &clock_manager_base->main_pll.vco);
264 
265 	uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
266 
267 	/* assert pheriph outresetall */
268 	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
269 	       &clock_manager_base->per_pll.vco);
270 
271 	/* assert sdram outresetall */
272 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
273 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
274 		&clock_manager_base->sdr_pll.vco);
275 
276 	/* deassert main outresetall */
277 	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
278 	       &clock_manager_base->main_pll.vco);
279 
280 	/* deassert pheriph outresetall */
281 	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
282 	       &clock_manager_base->per_pll.vco);
283 
284 	/* deassert sdram outresetall */
285 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
286 	       &clock_manager_base->sdr_pll.vco);
287 
288 	/*
289 	 * now that we've toggled outreset all, all the clocks
290 	 * are aligned nicely; so we can change any phase.
291 	 */
292 	cm_write_with_phase(cfg->ddrdqsclk,
293 			    (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
294 			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
295 
296 	/* SDRAM DDR2XDQSCLK */
297 	cm_write_with_phase(cfg->ddr2xdqsclk,
298 			    (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
299 			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
300 
301 	cm_write_with_phase(cfg->ddrdqclk,
302 			    (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
303 			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
304 
305 	cm_write_with_phase(cfg->s2fuser2clk,
306 			    (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
307 			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
308 
309 	/* Take all three PLLs out of bypass when safe mode is cleared. */
310 	cm_write_bypass(0);
311 
312 	/* clear safe mode */
313 	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
314 
315 	/*
316 	 * now that safe mode is clear with clocks gated
317 	 * it safe to change the source mux for the flashes the the L4_MAIN
318 	 */
319 	writel(cfg->persrc, &clock_manager_base->per_pll.src);
320 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
321 
322 	/* Now ungate non-hw-managed clocks */
323 	writel(~0, &clock_manager_base->main_pll.en);
324 	writel(~0, &clock_manager_base->per_pll.en);
325 	writel(~0, &clock_manager_base->sdr_pll.en);
326 
327 	/* Clear the loss of lock bits (write 1 to clear) */
328 	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
329 	       CLKMGR_INTER_MAINPLLLOST_MASK,
330 	       &clock_manager_base->inter);
331 }
332 
333 static unsigned int cm_get_main_vco_clk_hz(void)
334 {
335 	uint32_t reg, clock;
336 
337 	/* get the main VCO clock */
338 	reg = readl(&clock_manager_base->main_pll.vco);
339 	clock = cm_get_osc_clk_hz(1);
340 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
341 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
342 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
343 		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
344 
345 	return clock;
346 }
347 
348 static unsigned int cm_get_per_vco_clk_hz(void)
349 {
350 	uint32_t reg, clock = 0;
351 
352 	/* identify PER PLL clock source */
353 	reg = readl(&clock_manager_base->per_pll.vco);
354 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
355 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
356 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
357 		clock = cm_get_osc_clk_hz(1);
358 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
359 		clock = cm_get_osc_clk_hz(2);
360 	else if (reg == CLKMGR_VCO_SSRC_F2S)
361 		clock = cm_get_f2s_per_ref_clk_hz();
362 
363 	/* get the PER VCO clock */
364 	reg = readl(&clock_manager_base->per_pll.vco);
365 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
366 		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
367 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
368 		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
369 
370 	return clock;
371 }
372 
373 unsigned long cm_get_mpu_clk_hz(void)
374 {
375 	uint32_t reg, clock;
376 
377 	clock = cm_get_main_vco_clk_hz();
378 
379 	/* get the MPU clock */
380 	reg = readl(&clock_manager_base->altera.mpuclk);
381 	clock /= (reg + 1);
382 	reg = readl(&clock_manager_base->main_pll.mpuclk);
383 	clock /= (reg + 1);
384 	return clock;
385 }
386 
387 unsigned long cm_get_sdram_clk_hz(void)
388 {
389 	uint32_t reg, clock = 0;
390 
391 	/* identify SDRAM PLL clock source */
392 	reg = readl(&clock_manager_base->sdr_pll.vco);
393 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
394 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
395 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
396 		clock = cm_get_osc_clk_hz(1);
397 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
398 		clock = cm_get_osc_clk_hz(2);
399 	else if (reg == CLKMGR_VCO_SSRC_F2S)
400 		clock = cm_get_f2s_sdr_ref_clk_hz();
401 
402 	/* get the SDRAM VCO clock */
403 	reg = readl(&clock_manager_base->sdr_pll.vco);
404 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
405 		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
406 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
407 		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
408 
409 	/* get the SDRAM (DDR_DQS) clock */
410 	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
411 	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
412 	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
413 	clock /= (reg + 1);
414 
415 	return clock;
416 }
417 
418 unsigned int cm_get_l4_sp_clk_hz(void)
419 {
420 	uint32_t reg, clock = 0;
421 
422 	/* identify the source of L4 SP clock */
423 	reg = readl(&clock_manager_base->main_pll.l4src);
424 	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
425 	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
426 
427 	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
428 		clock = cm_get_main_vco_clk_hz();
429 
430 		/* get the clock prior L4 SP divider (main clk) */
431 		reg = readl(&clock_manager_base->altera.mainclk);
432 		clock /= (reg + 1);
433 		reg = readl(&clock_manager_base->main_pll.mainclk);
434 		clock /= (reg + 1);
435 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
436 		clock = cm_get_per_vco_clk_hz();
437 
438 		/* get the clock prior L4 SP divider (periph_base_clk) */
439 		reg = readl(&clock_manager_base->per_pll.perbaseclk);
440 		clock /= (reg + 1);
441 	}
442 
443 	/* get the L4 SP clock which supplied to UART */
444 	reg = readl(&clock_manager_base->main_pll.maindiv);
445 	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
446 	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
447 	clock = clock / (1 << reg);
448 
449 	return clock;
450 }
451 
452 unsigned int cm_get_mmc_controller_clk_hz(void)
453 {
454 	uint32_t reg, clock = 0;
455 
456 	/* identify the source of MMC clock */
457 	reg = readl(&clock_manager_base->per_pll.src);
458 	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
459 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
460 
461 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
462 		clock = cm_get_f2s_per_ref_clk_hz();
463 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
464 		clock = cm_get_main_vco_clk_hz();
465 
466 		/* get the SDMMC clock */
467 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
468 		clock /= (reg + 1);
469 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
470 		clock = cm_get_per_vco_clk_hz();
471 
472 		/* get the SDMMC clock */
473 		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
474 		clock /= (reg + 1);
475 	}
476 
477 	/* further divide by 4 as we have fixed divider at wrapper */
478 	clock /= 4;
479 	return clock;
480 }
481 
482 unsigned int cm_get_qspi_controller_clk_hz(void)
483 {
484 	uint32_t reg, clock = 0;
485 
486 	/* identify the source of QSPI clock */
487 	reg = readl(&clock_manager_base->per_pll.src);
488 	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
489 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
490 
491 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
492 		clock = cm_get_f2s_per_ref_clk_hz();
493 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
494 		clock = cm_get_main_vco_clk_hz();
495 
496 		/* get the qspi clock */
497 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
498 		clock /= (reg + 1);
499 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
500 		clock = cm_get_per_vco_clk_hz();
501 
502 		/* get the qspi clock */
503 		reg = readl(&clock_manager_base->per_pll.perqspiclk);
504 		clock /= (reg + 1);
505 	}
506 
507 	return clock;
508 }
509 
510 unsigned int cm_get_spi_controller_clk_hz(void)
511 {
512 	uint32_t reg, clock = 0;
513 
514 	clock = cm_get_per_vco_clk_hz();
515 
516 	/* get the clock prior L4 SP divider (periph_base_clk) */
517 	reg = readl(&clock_manager_base->per_pll.perbaseclk);
518 	clock /= (reg + 1);
519 
520 	return clock;
521 }
522 
523 static void cm_print_clock_quick_summary(void)
524 {
525 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
526 	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
527 	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
528 	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
529 	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
530 	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
531 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
532 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
533 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
534 	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
535 }
536 
537 int set_cpu_clk_info(void)
538 {
539 	/* Calculate the clock frequencies required for drivers */
540 	cm_get_l4_sp_clk_hz();
541 	cm_get_mmc_controller_clk_hz();
542 
543 	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
544 	gd->bd->bi_dsp_freq = 0;
545 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
546 
547 	return 0;
548 }
549 
550 int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
551 {
552 	cm_print_clock_quick_summary();
553 	return 0;
554 }
555 
556 U_BOOT_CMD(
557 	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
558 	"display clocks",
559 	""
560 );
561