1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Altera SoCFPGA common board code 4 * 5 * Copyright (C) 2015 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/clock_manager.h> 13 #include <asm/arch/misc.h> 14 #include <asm/io.h> 15 16 #include <usb.h> 17 #include <usb/dwc2_udc.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 void s_init(void) { 22 #ifndef CONFIG_ARM64 23 /* 24 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes 25 * is disabled in ACTLR. 26 * This is optional on CycloneV / ArriaV. 27 * This is mandatory on Arria10, otherwise Linux refuses to boot. 28 */ 29 asm volatile( 30 "mcr p15, 0, %0, c1, c0, 1\n" 31 "mcr p15, 0, %0, c1, c0, 2\n" 32 "isb\n" 33 "dsb\n" 34 ::"r"(0x0)); 35 #endif 36 } 37 38 /* 39 * Miscellaneous platform dependent initialisations 40 */ 41 int board_init(void) 42 { 43 /* Address of boot parameters for ATAG (if ATAG is used) */ 44 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 45 46 return 0; 47 } 48 49 int dram_init_banksize(void) 50 { 51 fdtdec_setup_memory_banksize(); 52 53 return 0; 54 } 55 56 #ifdef CONFIG_USB_GADGET 57 struct dwc2_plat_otg_data socfpga_otg_data = { 58 .usb_gusbcfg = 0x1417, 59 }; 60 61 int board_usb_init(int index, enum usb_init_type init) 62 { 63 int node[2], count; 64 fdt_addr_t addr; 65 66 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", 67 COMPAT_ALTERA_SOCFPGA_DWC2USB, 68 node, 2); 69 if (count <= 0) /* No controller found. */ 70 return 0; 71 72 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); 73 if (addr == FDT_ADDR_T_NONE) { 74 printf("UDC Controller has no 'reg' property!\n"); 75 return -EINVAL; 76 } 77 78 /* Patch the address from OF into the controller pdata. */ 79 socfpga_otg_data.regs_otg = addr; 80 81 return dwc2_udc_probe(&socfpga_otg_data); 82 } 83 84 int g_dnl_board_usb_cable_connected(void) 85 { 86 return 1; 87 } 88 #endif 89