1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Altera SoCFPGA common board code 4 * 5 * Copyright (C) 2015 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/clock_manager.h> 13 #include <asm/io.h> 14 15 #include <usb.h> 16 #include <usb/dwc2_udc.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 void s_init(void) {} 21 22 /* 23 * Miscellaneous platform dependent initialisations 24 */ 25 int board_init(void) 26 { 27 /* Address of boot parameters for ATAG (if ATAG is used) */ 28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 29 30 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 31 /* configuring the clock based on handoff */ 32 cm_basic_init(gd->fdt_blob); 33 #endif 34 35 return 0; 36 } 37 38 int dram_init_banksize(void) 39 { 40 fdtdec_setup_memory_banksize(); 41 42 return 0; 43 } 44 45 #ifdef CONFIG_USB_GADGET 46 struct dwc2_plat_otg_data socfpga_otg_data = { 47 .usb_gusbcfg = 0x1417, 48 }; 49 50 int board_usb_init(int index, enum usb_init_type init) 51 { 52 int node[2], count; 53 fdt_addr_t addr; 54 55 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", 56 COMPAT_ALTERA_SOCFPGA_DWC2USB, 57 node, 2); 58 if (count <= 0) /* No controller found. */ 59 return 0; 60 61 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); 62 if (addr == FDT_ADDR_T_NONE) { 63 printf("UDC Controller has no 'reg' property!\n"); 64 return -EINVAL; 65 } 66 67 /* Patch the address from OF into the controller pdata. */ 68 socfpga_otg_data.regs_otg = addr; 69 70 return dwc2_udc_probe(&socfpga_otg_data); 71 } 72 73 int g_dnl_board_usb_cable_connected(void) 74 { 75 return 1; 76 } 77 #endif 78