183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 28e535af2SMarek Vasut /* 38e535af2SMarek Vasut * Altera SoCFPGA common board code 48e535af2SMarek Vasut * 58e535af2SMarek Vasut * Copyright (C) 2015 Marek Vasut <marex@denx.de> 68e535af2SMarek Vasut */ 78e535af2SMarek Vasut 88e535af2SMarek Vasut #include <common.h> 98e535af2SMarek Vasut #include <errno.h> 10c960ef29STien Fong Chee #include <fdtdec.h> 118e535af2SMarek Vasut #include <asm/arch/reset_manager.h> 12c960ef29STien Fong Chee #include <asm/arch/clock_manager.h> 13011fa5f3STien Fong Chee #include <asm/arch/misc.h> 148e535af2SMarek Vasut #include <asm/io.h> 158e535af2SMarek Vasut 168e535af2SMarek Vasut #include <usb.h> 178e535af2SMarek Vasut #include <usb/dwc2_udc.h> 188e535af2SMarek Vasut 198e535af2SMarek Vasut DECLARE_GLOBAL_DATA_PTR; 208e535af2SMarek Vasut 21887a8b6eSMarek Vasut void s_init(void) { 228c9f247aSLey Foon Tan #ifndef CONFIG_ARM64 23887a8b6eSMarek Vasut /* 24*937db718SMarek Vasut * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes 25*937db718SMarek Vasut * is disabled in ACTLR. 26887a8b6eSMarek Vasut * This is optional on CycloneV / ArriaV. 27887a8b6eSMarek Vasut * This is mandatory on Arria10, otherwise Linux refuses to boot. 28887a8b6eSMarek Vasut */ 29887a8b6eSMarek Vasut asm volatile( 30887a8b6eSMarek Vasut "mcr p15, 0, %0, c1, c0, 1\n" 31*937db718SMarek Vasut "mcr p15, 0, %0, c1, c0, 2\n" 32887a8b6eSMarek Vasut "isb\n" 33887a8b6eSMarek Vasut "dsb\n" 34887a8b6eSMarek Vasut ::"r"(0x0)); 358c9f247aSLey Foon Tan #endif 36887a8b6eSMarek Vasut } 378e535af2SMarek Vasut 388e535af2SMarek Vasut /* 398e535af2SMarek Vasut * Miscellaneous platform dependent initialisations 408e535af2SMarek Vasut */ 418e535af2SMarek Vasut int board_init(void) 428e535af2SMarek Vasut { 438e535af2SMarek Vasut /* Address of boot parameters for ATAG (if ATAG is used) */ 448e535af2SMarek Vasut gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 458e535af2SMarek Vasut 46c960ef29STien Fong Chee #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 47c960ef29STien Fong Chee /* configuring the clock based on handoff */ 48c960ef29STien Fong Chee cm_basic_init(gd->fdt_blob); 49011fa5f3STien Fong Chee 50011fa5f3STien Fong Chee /* Add device descriptor to FPGA device table */ 51011fa5f3STien Fong Chee socfpga_fpga_add(); 52c960ef29STien Fong Chee #endif 53c960ef29STien Fong Chee 548e535af2SMarek Vasut return 0; 558e535af2SMarek Vasut } 568e535af2SMarek Vasut 5753faef1eSTien Fong Chee int dram_init_banksize(void) 5853faef1eSTien Fong Chee { 5953faef1eSTien Fong Chee fdtdec_setup_memory_banksize(); 6053faef1eSTien Fong Chee 6153faef1eSTien Fong Chee return 0; 6253faef1eSTien Fong Chee } 6353faef1eSTien Fong Chee 648e535af2SMarek Vasut #ifdef CONFIG_USB_GADGET 658e535af2SMarek Vasut struct dwc2_plat_otg_data socfpga_otg_data = { 668e535af2SMarek Vasut .usb_gusbcfg = 0x1417, 678e535af2SMarek Vasut }; 688e535af2SMarek Vasut 698e535af2SMarek Vasut int board_usb_init(int index, enum usb_init_type init) 708e535af2SMarek Vasut { 718e535af2SMarek Vasut int node[2], count; 728e535af2SMarek Vasut fdt_addr_t addr; 738e535af2SMarek Vasut 748e535af2SMarek Vasut count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", 758e535af2SMarek Vasut COMPAT_ALTERA_SOCFPGA_DWC2USB, 768e535af2SMarek Vasut node, 2); 778e535af2SMarek Vasut if (count <= 0) /* No controller found. */ 788e535af2SMarek Vasut return 0; 798e535af2SMarek Vasut 808e535af2SMarek Vasut addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); 818e535af2SMarek Vasut if (addr == FDT_ADDR_T_NONE) { 828e535af2SMarek Vasut printf("UDC Controller has no 'reg' property!\n"); 838e535af2SMarek Vasut return -EINVAL; 848e535af2SMarek Vasut } 858e535af2SMarek Vasut 868e535af2SMarek Vasut /* Patch the address from OF into the controller pdata. */ 878e535af2SMarek Vasut socfpga_otg_data.regs_otg = addr; 888e535af2SMarek Vasut 898e535af2SMarek Vasut return dwc2_udc_probe(&socfpga_otg_data); 908e535af2SMarek Vasut } 918e535af2SMarek Vasut 928e535af2SMarek Vasut int g_dnl_board_usb_cable_connected(void) 938e535af2SMarek Vasut { 948e535af2SMarek Vasut return 1; 958e535af2SMarek Vasut } 968e535af2SMarek Vasut #endif 97