xref: /openbmc/u-boot/arch/arm/mach-socfpga/Kconfig (revision e9c847c3)
1if ARCH_SOCFPGA
2
3config SPL_LIBCOMMON_SUPPORT
4	default y
5
6config SPL_LIBDISK_SUPPORT
7	default y
8
9config SPL_LIBGENERIC_SUPPORT
10	default y
11
12config SPL_MMC_SUPPORT
13	default y if DM_MMC
14
15config SPL_NAND_SUPPORT
16	default y if SPL_NAND_DENALI
17
18config SPL_SERIAL_SUPPORT
19	default y
20
21config SPL_SPI_FLASH_SUPPORT
22	default y if SPL_SPI_SUPPORT
23
24config SPL_SPI_SUPPORT
25	default y if DM_SPI
26
27config SPL_WATCHDOG_SUPPORT
28	default y
29
30config TARGET_SOCFPGA_ARRIA5
31	bool
32	select TARGET_SOCFPGA_GEN5
33
34config TARGET_SOCFPGA_CYCLONE5
35	bool
36	select TARGET_SOCFPGA_GEN5
37
38config TARGET_SOCFPGA_GEN5
39	bool
40
41choice
42	prompt "Altera SOCFPGA board select"
43	optional
44
45config TARGET_SOCFPGA_ARRIA5_SOCDK
46	bool "Altera SOCFPGA SoCDK (Arria V)"
47	select TARGET_SOCFPGA_ARRIA5
48
49config TARGET_SOCFPGA_CYCLONE5_SOCDK
50	bool "Altera SOCFPGA SoCDK (Cyclone V)"
51	select TARGET_SOCFPGA_CYCLONE5
52
53config TARGET_SOCFPGA_DENX_MCVEVK
54	bool "DENX MCVEVK (Cyclone V)"
55	select TARGET_SOCFPGA_CYCLONE5
56
57config TARGET_SOCFPGA_EBV_SOCRATES
58	bool "EBV SoCrates (Cyclone V)"
59	select TARGET_SOCFPGA_CYCLONE5
60
61config TARGET_SOCFPGA_IS1
62	bool "IS1 (Cyclone V)"
63	select TARGET_SOCFPGA_CYCLONE5
64
65config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
66	bool "samtec VIN|ING FPGA (Cyclone V)"
67	select TARGET_SOCFPGA_CYCLONE5
68
69config TARGET_SOCFPGA_SR1500
70	bool "SR1500 (Cyclone V)"
71	select TARGET_SOCFPGA_CYCLONE5
72
73config TARGET_SOCFPGA_TERASIC_DE0_NANO
74	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
75	select TARGET_SOCFPGA_CYCLONE5
76
77config TARGET_SOCFPGA_TERASIC_DE1_SOC
78	bool "Terasic DE1-SoC (Cyclone V)"
79	select TARGET_SOCFPGA_CYCLONE5
80
81config TARGET_SOCFPGA_TERASIC_SOCKIT
82	bool "Terasic SoCkit (Cyclone V)"
83	select TARGET_SOCFPGA_CYCLONE5
84
85endchoice
86
87config SYS_BOARD
88	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
89	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
90	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
91	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
92	default "is1" if TARGET_SOCFPGA_IS1
93	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
94	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
95	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
96	default "sr1500" if TARGET_SOCFPGA_SR1500
97	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
98
99config SYS_VENDOR
100	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
101	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
102	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
103	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
104	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
105	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
106	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
107	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
108
109config SYS_SOC
110	default "socfpga"
111
112config SYS_CONFIG_NAME
113	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
114	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
115	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
116	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
117	default "socfpga_is1" if TARGET_SOCFPGA_IS1
118	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
119	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
120	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
121	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
122	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
123
124endif
125